DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5 and 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US 2024/0364283 A1, hereinafter "Zhou") in view of Fleischer (US 2014/0191797 A1, hereinafter "Fleischer").
Regarding claim 1, Zhou teaches a wireless transmission circuit (integrated circuit 12 with DBB processor 11 and antenna 13; FIG. 1A, ¶0073) comprising:
a power amplifier circuit configured to amplify a radio frequency (RF) signal modulated in a plurality of modulation symbols (transmitter 1211 converts the baseband modulation signal to a high-frequency RF signal, ¶¶0074–0075; the symbols are OFDM symbols n, n+1, n+2, n+3, ¶0070 and FIG. 1C) based on an average power tracking (APT) voltage (power supply voltage Vout, dynamically adjusted at the symbol level by symbol power tracking, ¶0072, ¶0082);
a transceiver circuit (DBB processor 11 and transceiver 121; FIG. 1A, ¶¶0073–0074) configured to generate a target voltage (reference signal Vref, which "is proportional to the target power supply voltage of the PA 123 at each symbol," ¶0075; also ¶0085) in accordance with a time-variant power envelope of the RF signal (the output supply voltage changes "based on a change of an envelope signal of the power amplifier," ¶0007; envelope tracking signal, ¶0074); and
a power management integrated circuit (PMIC) (power amplifier power supply circuit 122 / fast adjustment power supply circuit 20 within integrated circuit 12, ¶¶0073, 0079; controller 2051 implemented as an ASIC, SoC or the like, ¶0122) comprising:
a voltage generation circuit (first power supply circuit 201, a buck DC-DC converter, ¶0092; FIG. 3) configured to generate the APT voltage in each of the plurality of modulation symbols based on the target voltage (Vout regulated to the target supply voltage indicated by Vref at each symbol, ¶¶0075, 0082–0083); and
a control circuit (second power supply circuit 200, the fast current charger, comprising main power supply branch 203 with first gate driving circuit 2032, together with control circuit 205; ¶¶0079, 0088, 0095–0097) configured to:
determine that the target voltage indicates one or more increased levels of the APT voltage in a respective one of the plurality of modulation symbols (CMP1 determines that reference signal Vref "has a rise jump" to a first target voltage while sampling voltage Vfb remains below it, ¶¶0084, 0098–0101; FIG. 5A); and
control the voltage generation circuit to increase the APT voltage from the average level to each of the one or more increased levels within a defined temporal limit (main branch 203 outputs a first charge current to the output end of first power supply circuit 201 "to accelerate the jump of the power supply voltage that tracks a reference signal of the power amplifier, and shorten jump time," ¶¶0011, 0083, 0085; the jump must complete within the symbol time interval of approximately 290 ns, ¶0072).
Zhou is silent to teaching that wherein the one or more increased levels of the APT voltage being relative to an average level of the APT voltage.
In the same field of endeavor, Fleischer teaches a device wherein the one or more increased levels of the APT voltage being relative to an average level of the APT voltage (Fleischer teaches holding the PA supply at a base/average level (Vdd = 3.3 V, ¶0043 and Table 1) and increasing it to one or more increased levels (Table 1 "Target level" values 4.95 V, 5.775 V, 6.1875 V, 6.39375 V; ¶0045) during transmission whenever the time-variant envelope exceeds a threshold, returning to the base level otherwise (¶¶0029, 0055–0056; FIGS. 9–10)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to configure Zhou's control circuit to further increase the supply voltage, within a given symbol, from that symbol's average level to one or more increased levels indicated by the target voltage, as taught by Fleischer. Both references address the same problem — supply headroom wasted during the off-peak portions of a high-PAPR waveform (Zhou ¶¶0071–0072; Fleischer ¶¶0002–0005, 0032). Fleischer identifies the specific benefit of doing so intra-symbol: on the order of 6–10 dB of supply savings while preserving linearity at the transmitted peak (¶¶0032, 0059). Zhou's fast current charger is already configured to complete supply jumps inside a ~290 ns window (¶¶0072, 0083), so it would predictably accommodate additional intra-symbol jumps. The combination is the use of a known technique (threshold-triggered intra-symbol boosting) to improve a similar device (Zhou's symbol-level supply) in the same way, with predictable results. KSR, 550 U.S. 398.
Regarding claim 2, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 1, wherein the transceiver circuit is further configured to:
compare the time-variant power envelope of the RF signal against a predefined power threshold; indicate the one or more increased levels of the APT voltage in the target voltage whenever the time-variant power envelope is higher than the predefined power threshold (Fleischer teaches,¶0055, FIG. 9: supply increased tracking the amount in excess of Th; ¶0056, FIG. 10: supply increased to Vmax above Th); and indicate the average level of the APT voltage in the target voltage whenever the time-variant power envelope is lower than or equal to the predefined power threshold (Fleischer teaches, ¶0029: the boost transistor is "switched on only when the input signal to the amplifier exceeds a threshold"; FIGS. 9–10 show the flat base level below Th).
Regarding claim 3, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 2, wherein the transceiver circuit comprises:
a digital baseband circuit configured to generate a digital signal associated with a time-variant amplitude envelope (Zhou: DBB processor 11 outputs the low-frequency baseband modulation signal (¶0074). Fleischer: digital baseband signal 20, the amplitude envelope being the sum of the I and Q channels (¶¶0036, 0044));
a modulator circuit configured to convert the digital signal into the RF signal associated with the time-variant power envelope (Zhou: transmitter 1211 "configured to convert a low-frequency baseband signal into a high-frequency radio frequency signal" (¶0075). Fleischer: mixing circuit 11 with local oscillator 9 (¶0036, FIG. 3));
an envelope detection circuit configured to compare the time-variant amplitude envelope against the predefined power threshold (Fleischer: threshold detection of the input signal envelope against Th (¶¶0029, 0055–0056; FIGS. 9–10));
a target voltage circuit configured to generate a digital target voltage to: indicate the one or more increased levels of the APT voltage whenever the time-variant power envelope is higher than the predefined power threshold; and indicate the average level of the APT voltage whenever the time-variant power envelope is lower than or equal to the predefined power threshold (Zhou: DBB 11 determines the target power supply voltage of the PA at each symbol and outputs the corresponding reference signal (¶¶0074–0075). Fleischer: the MSB decode that selects among the base level and the Table 1 target levels (¶¶0044–0045, Table 1)); and
a digital-to-analog converter, DAC, configured to convert the digital target voltage into an analog target voltage (Zhou: the reference signal is output to the power supply circuit "by using a digital-to-analog converter (DAC)" (¶0074)).
Regarding claim 5, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 3, wherein the transceiver circuit is further configured to generate the target voltage comprising the digital target voltage (Zhou's target voltage comprises the digital target voltage: the target power supply voltage for each symbol is determined and held digitally in the DBB processor 11 before conversion (¶0074). Fleischer likewise controls the boost "in open-loop with the digital data of the baseband signal" (¶0040), the digital MSB copy being delivered directly to driver 4 (¶¶0009, 0044)).
Regarding claim 10, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 3, wherein the transceiver circuit is further configured to generate the target voltage comprising the analog target voltage (Zhou's target voltage comprises the analog target voltage: the reference signal Vref supplied to the power supply circuit is the analog output of the DAC (¶0074) and is used in analog form as the input to error amplifier 206 (non-inverting input, ¶0104) and as the basis for Vref1/Vref2 at comparators CMP1/CMP2 (¶¶0098–0100)).
Regarding claim 11, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 10, wherein, for each of the one or more increased levels of the APT voltage, the control circuit is further configured to:
generate one or more acceleration currents from the analog target voltage; and inject the one or more acceleration currents into one or more selected injection points to thereby cause the voltage generation circuit to increase the APT voltage from the average level to a respective one of the one or more increased levels within the defined temporal limit (Zhou teaches the main power supply branch 203 outputs a first charge current, and auxiliary power supply branch 204 outputs a second charge current, to the output end of first power supply circuit 201 (¶¶0083–0087). Those currents are generated as a function of the analog reference signal — CMP1/CMP2 compare Vfb against Vref1/Vref2, both "obtained based on the reference signal" (¶0100; also ¶¶0097–0101), and error amplifier 206 compares Vfb against Vref directly (¶¶0103–0104). The stated purpose is to "accelerate completion of a rise jump of the power supply voltage Vout" (¶0085) within the ~290 ns symbol interval (¶0072)).
Regarding claim 12, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 11, wherein the control circuit comprises an acceleration circuit configured to generate the one or more acceleration currents based on the analog target voltage and inject the one or more acceleration currents into the one or more selected injection points (Zhou's control circuit comprises an acceleration circuit — the second power supply circuit 200 (fast current charger), comprising main branch 203 (main charging transistor P1 and main discharging transistor N1 with first gate driving circuit 2032, ¶¶0095–0097) and auxiliary branch 204 (auxiliary charging transistor P2 and auxiliary discharging transistor N2 with second gate driving circuit 2041, ¶¶0108–0110) — which generates the charge currents based on the analog reference signal and injects them at the selected point).
Regarding claim 13, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 12, wherein the one or more selected injection points comprise one or more of a voltage loop control, a current loop control, and an output of the voltage generation circuit (Zhou injects at the output of the voltage generation circuit: both branches deliver current "to the output end of the first power supply circuit 201" (¶¶0083, 0086), the connection points Z1 and Z2 being coupled to the power supply end of the PA and to that output (¶¶0096, 0108; FIG. 3)).
Regarding claim 14, Zhou teaches a method for accelerating intra-symbol voltage change comprising:
amplifying a radio frequency (RF) signal modulated in a plurality of modulation symbols based on an average power tracking (APT) voltage (transmitter 1211 converts the baseband modulation signal to a high-frequency RF signal, ¶¶0074–0075; the symbols are OFDM symbols n, n+1, n+2, n+3, ¶0070 and FIG. 1C) based on an average power tracking (APT) voltage (power supply voltage Vout, dynamically adjusted at the symbol level by symbol power tracking, ¶0072, ¶0082);
generating a target voltage in accordance with a time-variant power envelope of the RF signal (reference signal Vref, which "is proportional to the target power supply voltage of the PA 123 at each symbol," ¶0075; also ¶0085) in accordance with a time-variant power envelope of the RF signal (the output supply voltage changes "based on a change of an envelope signal of the power amplifier," ¶0007; envelope tracking signal, ¶0074);
generating the APT voltage in each of the plurality of modulation symbols based on the target voltage (Vout regulated to the target supply voltage indicated by Vref at each symbol, ¶¶0075, 0082–0083);
determining that the target voltage indicates one or more increased levels of the APT voltage in a respective one of the plurality of modulation symbols (CMP1 determines that reference signal Vref "has a rise jump" to a first target voltage while sampling voltage Vfb remains below it, ¶¶0084, 0098–0101; FIG. 5A); and
increasing the APT voltage from the average level to each of the one or more increased levels within a defined temporal limit (main branch 203 outputs a first charge current to the output end of first power supply circuit 201 "to accelerate the jump of the power supply voltage that tracks a reference signal of the power amplifier, and shorten jump time," ¶¶0011, 0083, 0085; the jump must complete within the symbol time interval of approximately 290 ns, ¶0072).
Zhou is silent to teaching that wherein the one or more increased levels of the APT voltage being relative to an average level of the APT voltage.
In the same field of endeavor, Fleischer teaches a method wherein the one or more increased levels of the APT voltage being relative to an average level of the APT voltage (Fleischer teaches holding the PA supply at a base/average level (Vdd = 3.3 V, ¶0043 and Table 1) and increasing it to one or more increased levels (Table 1 "Target level" values 4.95 V, 5.775 V, 6.1875 V, 6.39375 V; ¶0045) during transmission whenever the time-variant envelope exceeds a threshold, returning to the base level otherwise (¶¶0029, 0055–0056; FIGS. 9–10)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to configure Zhou's control circuit to further increase the supply voltage, within a given symbol, from that symbol's average level to one or more increased levels indicated by the target voltage, as taught by Fleischer. Both references address the same problem — supply headroom wasted during the off-peak portions of a high-PAPR waveform (Zhou ¶¶0071–0072; Fleischer ¶¶0002–0005, 0032). Fleischer identifies the specific benefit of doing so intra-symbol: on the order of 6–10 dB of supply savings while preserving linearity at the transmitted peak (¶¶0032, 0059). Zhou's fast current charger is already configured to complete supply jumps inside a ~290 ns window (¶¶0072, 0083), so it would predictably accommodate additional intra-symbol jumps. The combination is the use of a known technique (threshold-triggered intra-symbol boosting) to improve a similar device (Zhou's symbol-level supply) in the same way, with predictable results. KSR, 550 U.S. 398.
Regarding claims 15, 16, 19, 20, the dependent claims are interpreted and rejected for the same reasons as set forth above in claims 3, 5, 10 and 13, respectively.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Fleischer as applied to claim 3 above, and further in view of Kasargod (US 2021/0203369 A1).
Regarding claim 4, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 3.
The combination of Zhou and Fleischer is silent to teaching that wherein the transceiver circuit further comprises a digital predistortion (DPD) circuit coupled between the digital baseband circuit and the modulator circuit, the DPD circuit is configured to pre-distort the digital signal to thereby correct one or more of an amplitude-amplitude (AMAM) distortion and an amplitude-phase, AMPM, distortion in the RF signal.
In the same field of endeavor, Kasargod teaches a device wherein the transceiver circuit further comprises a digital predistortion (DPD) circuit coupled between the digital baseband circuit (DPD processor 123 receives the digital baseband data signal 102 as a time-domain symbol stream from IFFT block 122, ¶¶0027, 0036; FIGS. 1, 6) and the modulator circuit (The pre-distorted digital baseband signal 103 is output to up-converter component 130 — DAC 131, mixer 132, LO 133 — which modulates the LO signal 106 to produce RF signal 105, ¶0028; FIG. 1), the DPD circuit is configured to pre-distort the digital signal to thereby correct one or more of an amplitude-amplitude (AMAM) distortion and an amplitude-phase, AMPM, distortion in the RF signal (Expressly "AM-to-PM (AM/PM) distortion," ¶0030, FIG. 4B; phase pre-distortion function FIG. 4D; AM/PM LUT 156, ¶¶0038–0039).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transmitter of Zhou to include the digital pre-distortion component of Kasargod, coupled between the digital baseband processor and the up-conversion/modulator path, in order to compensate for the amplitude-to-amplitude (AM/AM) and amplitude-to-phase (AM/PM) distortion of the power amplifier and thereby preserve linearity while retaining the efficiency gain that Zhou's symbol-level supply adjustment provides.
One of ordinary skill would therefore have been motivated by Kasargod's own teaching to apply its pre-distortion component to Zhou's transmitter, because doing so permits Zhou's supply voltage to be reduced further, and held closer to the instantaneous requirement, without incurring the amplitude and phase errors that Zhou's stated linearity premise would otherwise forbid. The modification is a combination of prior art elements according to known methods to yield the predictable result of an efficient transmitter with corrected PA distortion, and the use of a known technique (digital pre-distortion) to improve a similar device (a variable-envelope RF transmitter) in the same way. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007); MPEP 2143(A), (C).
Claim(s) 6, 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Fleischer as applied to claims 5 and 16 above, and further in view of Balteanu (US 2021/0218370 A1).
Regarding claim 6, the combination of Zhou and Fleischer teaches the wireless transmission circuit of claim 5.
The combination of Zhou and Fleischer is silent to teaching that wherein, for each of the one or more increased levels of the APT voltage, the control circuit is further configured to: determine a sequence of voltage change segments each associated with a respective one of a sequence of voltage damping factors organized in an ascending order; and control the voltage generation circuit to increase the APT voltage from the average level to a respective one of the one or more increased levels in accordance with the sequence of voltage damping factors.
In the same field of endeavor, Balteanu teaches a device wherein, for each of the one or more increased levels of the APT voltage, the control circuit is further configured to:
determine a sequence of voltage change segments each associated with a respective one of a sequence of voltage damping factors organized in an ascending order (¶0112; FIG. 5B — the transition is executed as an ordered series of switch activations Sw6_n, Sw6_c, Sw6_b, Sw6_a, each defining a distinct interval of the transition; ¶0108 separate control of each switch each associated with a respective one of a sequence of voltage damping factors; ¶¶0106–0107 — each path "is associated with different resistance," the series resistance being the damping element that suppresses the ringing of ¶0104; ¶0108 "gradually changing the resistance"; organized in an ascending order; FIG. 5B ordering (n first → a last) makes total resistance, and therefore damping, decrease monotonically across the sequence); and
control the voltage generation circuit to increase the APT voltage from the average level to a respective one of the one or more increased levels in accordance with the sequence of voltage damping factors (¶¶0087, 0106 — the sequence is what carries the supply from one regulated voltage level to a different regulated voltage level; ¶0094/¶0087 the MLS control circuit selects levels based on the envelope signal; ¶¶0088, 0095 the same modulator operates in an APT mode as well as an ET mode).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power amplifier power supply circuit of Zhou so that the transition of the power supply voltage from one level to a higher level is carried out through a sequence of progressively lower-resistance conduction paths, each associated with a different degree of damping, as taught by Balteanu, in order to reduce the overvoltage and ringing that Zhou's fast current injection would otherwise produce and thereby shorten the net settling time within the symbol interval. One of ordinary skill would have been motivated to apply Balteanu's graded, sequenced conduction paths to Zhou's charging and discharging transistors in order to obtain Balteanu's stated benefit — a supply transition with reduced overshoot and ringing — in the very circuit in which Zhou identifies overshoot as a consequence to be compensated. Doing so reduces the excursion that Zhou's auxiliary branch 204 must correct, shortens the total time to settle within the target band, and thereby directly serves Zhou's stated objective of completing the jump within the symbol interval. The modification is a combination of prior art elements according to known methods yielding predictable results, and the use of a known technique to improve a similar device in the same way. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007); MPEP 2143(A), (C).
Regarding claim 7, the combination of Zhou, Fleischer and Balteanu teaches the wireless transmission circuit of claim 6, wherein the sequence of voltage change segments comprises:
an over-damped segment associated with a smallest one of the sequence of voltage damping factors (The first-activated path, switch 201n/206n with the most series resistors 221n1…221nm — highest resistance, most heavily damped; FIG. 5B (Sw6_n first); ¶0115);
a critical-damped segment with an intermediate one of the sequence of voltage damping factors (The intermediate paths — switch 201c with resistors 221c1 and 221c2, and switch 201b with resistor 221b — activated after n and before a; ¶0107; FIG. 5B (Sw6_c, then Sw6_b)); and
an under-damped segment with a highest one of the sequence of voltage damping factors (The last-activated path, switch 201a with no series resistor — lowest resistance, least damped, the condition ¶0104 associates with "current ringing"; FIG. 5B (Sw6_a last)).
Regarding claim 17, the dependent claim is interpreted and rejected for the same reason as set forth above in claim 7.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou, Fleischer and Balteanu as applied to claim 6 above, and further in view of Zhang (US 2017/0248996 A1).
Regarding claim 8, the combination of Zhou, Fleischer and Balteanu teaches the wireless transmission circuit of claim 6, wherein the control circuit comprises:
a timer configured to generate the sequence of voltage change segments (Balteanu teaches Control circuit 320, FIG. 6: "delay elements 301, 302, 303, 304, 305, 306 and logical AND gates 316a, 316b, … 316n"; the AND gates "perform AND operations of delayed versions of the input signal SW6_in to generate switch control signals Sw6_a, Sw6_b, … Sw6_n" (¶¶0116–0117). Alternative control circuit 340, FIG. 7: "a shift register 331 … processes a clock signal CLK and an input signal SW6_in to generate multiple delayed versions" (¶¶0119–0120). Control circuit 350, FIG. 8: AND gates "associated with different resistances to provide delay between the switch control signals" (¶0122); the clocked shift-register embodiment is the cleanest timer of record);
a lookup table (LUT), configured to store multiple loop coefficient values (Balteanu teaches the MLS control circuit 74/210/320/340/350 does determine and apply the damping sequence (¶¶0090, 0108, 0116–0122)).
The combination of Zhou, Fleischer and Balteanu is silent to teaching that wherein the control circuit comprises:
a lookup table (LUT), configured to store multiple loop coefficient values; and a voltage loop control configured to control the voltage generation circuit to increase the APT voltage from the average level to the respective one of the one or more increased levels in accordance with the sequence of voltage damping factors.
In the same field of endeavor, Zhang teaches a device wherein the control circuit comprises:
a lookup table (LUT), configured to store multiple loop coefficient values (Zhang teaches: ¶0063 — PID filter coefficients (K<sub>P</sub>, K<sub>I</sub>, K<sub>D</sub>, K<sub>HPOLE</sub>) "are stored as a matrix of parameters within memory 144."; ¶0064, FIG. 9 — "three dimensional parameter matrix 146 configured [for] storing sets of the PID filter coefficients"; "Each block 148 of the parameter matrix 146 stores one set of PID filter coefficients."; ¶0065, Table 1 — "parameter matrix 146 could be alternatively illustrated and described as one or more two-dimensional look-up tables, which receive phase current and phase count information as inputs and return a corresponding set of PID filter coefficients"; sets K11 … K<sub>MN</sub>. The coefficients are loop coefficients on the reference's own terms: PID filters are "commonly used control loop feedback mechanisms" (¶0059), and the retrieved values are "updated into control loop registers … to optimize the voltage control loop implemented within the digital compensator 132" (¶0068)); and
a voltage loop control configured to control the voltage generation circuit to increase the APT voltage from the average level to the respective one of the one or more increased levels in accordance with the sequence of voltage damping factors (Zhang teaches: ¶¶0057–0058 — AVP module 134 decodes the VID command, computes V<sub>TARGET</sub> = VID − Load line·I<sub>SUM</sub> (EQ. 2), and subtracts V<sub>OUT</sub> to generate error signal (e). ¶0059 — digital compensator 132 / PID filter 142 filters the error and supplies multiphase PWM 136, "varying the pulse width and/or the pulse frequency of the PWM signals supplied to the voltage regulator phases 114."¶0068 — "the voltage control loop implemented within the digital compensator 132.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the control circuit of Zhou so that the control parameters governing the supply transition are predetermined and stored as sets in a look-up table indexed to operating variables, and retrieved and loaded into the control loop as operating conditions change, as taught by Zhang, in order to obtain fast, deterministic parameter selection that maintains loop stability across the operating range while preserving the rapid transient response Zhou requires.
A person of ordinary skill would have been motivated to implement Zhou's parameter selection in the manner Zhang teaches because Zhang states the benefit that Zhou needs: the stored parameter sets are chosen "so as to provide a phase margin above 60 degrees and a loop bandwidth that is approximately ⅕ of the switching frequency," which "enables the system to achieve stable operation in both static and dynamic loading conditions, and to respond very fast when there is a transient event" (¶0060). Zhou must complete each supply jump within a symbol time interval of approximately 290 nanoseconds (¶0072) while avoiding "circuit oscillation and repeated charge and discharge," a risk Zhou addresses only coarsely by widening its comparison thresholds by a variation Δ (¶0090). Retrieving a predetermined, stability-validated parameter set in a single clock, rather than computing or fixing one, serves both objectives at once. This is the use of a known technique to improve a similar device in the same way, yielding predictable results. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007); MPEP 2143(C), (D).
Allowable Subject Matter
Claims 9 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0075372 A1, US 2020/0304082.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEN WU HUANG whose telephone number is (571)272-7852. The examiner can normally be reached Mon-Fri 10-6.
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/WEN W HUANG/ Primary Examiner, Art Unit 2648
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