DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 31 and 33 are objected to because of the following informalities: The instances of the word “angel” should be changed to “angle”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 9, 15, 26, 28, 31, and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Du et al. (WO 2021/102769, translation attached herewith).
Regarding claim 1, Du discloses an array substrate (see figures 1a-5, for instance), comprising: a substrate (21) and a first wiring layer disposed on a side of the substrate, wherein the first wiring layer includes a plurality of gate lines (211) arranged at intervals in a first direction, and at least one gate line (211, portion that extends horizontally) extends in a second direction; the first direction (vertical) intersects with the second direction (horizontal); a second wiring layer disposed on a side of the first wiring layer away from the substrate, wherein the second wiring layer includes a plurality of data lines (212) arranged at intervals in the second direction, at least one data line extends in the first direction (vertical); an orthographic projection of a gate line (211) of the plurality of gate lines on the substrate intersects with an orthographic projection of a data line (212) of the plurality of data lines on the substrate (see figure 3a, for instance), two adjacent gate lines (211) of the plurality of gate lines and two adjacent data lines (212) of the plurality of data lines define a dimming region (20), and the dimming region is configured to switch between a sharing state and a privacy protection state; a first electrode layer (213) disposed on a side of the second wiring layer away from the substrate, wherein the first electrode layer (213) includes a plurality of first electrodes, and a first electrode is at least partially located in the dimming region (20); and a second electrode layer (214) disposed on a side of the first electrode layer away from the substrate (21), wherein the second electrode layer includes a second electrode (214), and an orthographic projection of the second electrode (214) on the substrate (21) is at least partially non-overlapping (at least at portions 2130 of figure 3a, for instance) with an orthographic projection of the first electrode (213) on the substrate (21).
Regarding claim 2, Du discloses the array substrate according to claim 1, wherein each-the dimming region (20) is provided with a thin film transistor (215) therein; the thin film transistor (215) is electrically connected to a gate line (211) of the two adjacent gate lines, a data line (212) of the two adjacent data lines and the first electrode, and configured to transmit a data signal from the data line to the first electrode under control of a scanning signal from the gate line; and the second electrode (214) include a plurality of avoidance openings, and each of the dimming region is provided with an avoidance opening (edges of 214) therein; an orthographic projection of the avoidance opening on the substrate at least partially overlaps with an orthographic projection of the thin film transistor (215) on the substrate.
Regarding claim 9, Du discloses the array substrate according to claim 1, wherein the second electrode includes: a plurality of third electrode strips arranged at intervals in the second direction and extending in the first direction (see figures 3b and 3c, for instance); and fourth electrode strips connected to ends of the plurality of third electrode strips, wherein an extension direction of a fourth electrode strip is parallel to an extension direction of the gate line (211), and an orthographic projection of the fourth electrode strip on the substrate at least partially overlaps with the orthographic projection of the gate line (211) on the substrate (21).
Regarding claim 15, Du discloses the array substrate according to claim 1, wherein in the dimming region (20), the first electrode (213) includes: a plurality of first electrode strips (see figure 3b) arranged at intervals in the second direction and extending in the first direction; and a second electrode (214) strip of which two ends are connected to each other, wherein the second electrode strip is connected to two ends of a first electrode strip of the plurality of first electrode strips in the first direction to form a structure in which the second electrode strip encloses the plurality of first electrode strips (see figures 3a-3b, for instance).
Regarding claim 26, Du discloses the array substrate according to one of claim 1, wherein the gate line (211) includes a plurality of extension sections (see figure 3a, for instance), and the plurality of extension sections include a plurality of first extension sections and a plurality of second extension sections that are alternately connected; a first extension section and a second extension section that are connected to each other are symmetrically arranged about a first reference line, and an included angle between an extension direction of the first extension section and the second direction or between an extension direction of the second extension direction and the second direction is in a range of 53° to 73°, inclusive; the first reference line is parallel to the first direction; and/or the data line (212) is routed along a broken line and includes a plurality of third extension sections and a plurality of fourth extension sections that are alternately arranged and connected in the first direction; a third extension section and a fourth extension section that are connected to each other are symmetrically arranged about a second reference line, and an included angle between an extension direction of the third extension section and the first direction or between an extension direction of the fourth extension direction and the first direction is in a range of 5° to 10°, inclusive; the second reference line is parallel to the second direction (see figure 3a, for instance).
Regarding claim 28, Du discloses the array substrate according to claim 1, wherein the second wiring layer further includes a plurality of common voltage signal (218) lines arranged at intervals in the first direction; and in the second direction, the plurality of data lines (212) and the plurality of common voltage signal lines (218) are alternately arranged, and a data line (212) and an adjacent common voltage signal line (218) are symmetrically arranged; or the second wiring laver further includes the plurality of common voltage signal lines (218) arranged at intervals in the first direction; in the second direction, the plurality of data lines (212) and the plurality of common voltage signal lines (218) are alternately arranged, and a data line (212) and an adjacent common voltage signal line (218) are symmetrically arranged: a common voltage signal line (218) of the plurality of common voltage signal lines includes a widened portion, the widened portion is electrically connected to the second electrode (214), and an orthographic projection of the widened portion on the substrate (21) is located in the orthographic projection of the gate line (211) on the substrate (21).
Regarding claim 31, Du discloses a view angle control cell, comprising: the array substrate according to claim 1, wherein the array substrate (21) includes a plurality of thin film transistors (215), and each dimming region (20) is provided with a thin film transistor therein (215); the thin film transistor (215) is configured to control the dimming region of the view angle control cell to switch between a sharing state and a privacy protection state; an opposite substrate (22) arranged opposite to the array substrate (21), wherein the opposite substrate (22) and the array substrate (21) define a liquid crystal cell (23); and a first-liquid crystal layer (23) located in the liquid crystal cell, wherein the liquid crystal layer is configured to, under control of a driving circuit of the array substrate (21), adjust deflection directions of liquid crystal molecules in the first-liquid crystal layer (23) and located in each dimming region (20) to control light entering each dimming region to be emitted from the liquid crystal layer (23) in the privacy protection state or the sharing state.
Regarding claim 33, Du discloses a display apparatus, comprising: the view angle control cell according to claim 31, a backlight module (“the backlight module is shown by the dotted arrow in the figure” of figure 1a) disposed on a side of the view angle control cell (2’) proximate to the array substrate (21) and configured to output light, whose propagation direction is perpendicular to the view angle control cell, toward a direction approaching the view angle control cell; and a liquid crystal display panel (1’) disposed on a side of the view angle control cell (2’) away from the backlight module.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Du in view of Su et al. (US 2019/0172844).
Regarding claim 3, Du discloses the array substrate according to claim 2. However, Du does not expressly disclose wherein the thin film transistor includes: a gate pattern disposed in the first wiring layer and connected to the gate line; a semiconductor pattern disposed between the first wiring layer and the second wiring layer; a source pattern disposed in the second wiring layer and connected to the data line; and a drain pattern disposed in the second wiring layer and spaced apart from the source pattern, wherein an orthographic projection of the drain pattern on the substrate is non-overlapping with the orthographic projection of the first electrode on the substrate; and an orthographic projection of the gate pattern on the substrate covers orthographic projections of the semiconductor pattern and the source pattern on the substrate, and partially overlaps with the orthographic projection of the drain pattern on the substrate; the orthographic projection of the avoidance opening on the substrate partially overlaps with the orthographic projections of the gate pattern, the semiconductor pattern, and the source pattern on the substrate, and covers the orthographic projection of the drain pattern on the substrate.
Su discloses an array substrate (see figures 1A-3B for instance), wherein the thin film transistor includes: a gate pattern (10) disposed in the first wiring layer and connected to the gate line (11); a semiconductor pattern (50) disposed between the first wiring layer (10) and the second wiring layer (30); a source pattern (30) disposed in the second wiring layer and connected to the data line; and a drain pattern (20) disposed in the second wiring layer and spaced apart from the source pattern, wherein an orthographic projection of the drain pattern on the substrate is non-overlapping with the orthographic projection of the first electrode on the substrate; and an orthographic projection of the gate pattern on the substrate covers orthographic projections of the semiconductor pattern and the source pattern on the substrate (see figure 2, for instance), and partially overlaps with the orthographic projection of the drain pattern on the substrate (see figure 3B, for instance); the orthographic projection of the avoidance opening on the substrate partially overlaps with the orthographic projections of the gate pattern, the semiconductor pattern, and the source pattern on the substrate (see figure 2, for instance, since the edge of each pixel excludes the gate pattern, the semiconductor pattern and the source pattern), and covers the orthographic projection of the drain pattern on the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the TFT structure of Su in the device of Du. The motivation for doing so would have been to decrease the power consumption of the array substrate and the display panel, as taught by Su ([0115]).
Claim(s) 30 is rejected under 35 U.S.C. 103 as being unpatentable over Du in view of Hsu et al. (CN 108873508A; translation attached herewith).
Regarding claim 30, Du discloses the array substrate according to claim 29. However, Du does not expressly disclose wherein the array substrate comprises a display area and a peripheral area surrounding the display area, and the array substrate further comprises: a common voltage signal bus line located in the peripheral area and surrounding the display area, wherein ease where the array substrate further comprises a common voltage signal line, an end of the common voltage signal line in the first direction is connected to the common voltage signal bus line; a gate driving circuit located in the peripheral area, wherein the gate driving circuit is disposed on at least one side of the display area in the second direction and electrically connected to the gate line; a fan-out trace located in the peripheral area, wherein the fan-out trace is disposed on a side of the display area in the first direction and electrically connected to the data line; a chip on film connected to the fan-out trace; and a driver chip bonded to the chip on film.
Hsu discloses an array substrate (see figures 4A-5, for instance), wherein the array substrate comprises a display area and a peripheral area surrounding the display area (see figure 5, for instance), and the array substrate further comprises: a common voltage signal bus line (F11) located in the peripheral area and surrounding the display area, wherein ease where the array substrate further comprises a common voltage signal line (154), an end of the common voltage signal line (154) in the first direction is connected to the common voltage signal bus line (F11); a gate driving circuit located in the peripheral area, wherein the gate driving circuit is disposed on at least one side of the display area in the second direction and electrically connected to the gate line (SL); a fan-out trace (see figure 5) located in the peripheral area, wherein the fan-out trace is disposed on a side of the display area in the first direction and electrically connected to the data line (DL) ; a chip on film connected to the fan-out trace; and a driver chip bonded to the chip on film (P1, P2, P3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the fan-out and chip structure of Hsu in the device of Du. The motivation for doing so would have been to reduce the use of the mask, so as to reduce the cost of manufacturing the array substrate, as taught by Hsu (see Summary of Invention).
Allowable Subject Matter
Claims 4, 6, 10-11, 14, 16-17, 19 and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHANAEL R BRIGGS whose telephone number is (571)272-8992. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/NATHANAEL R BRIGGS/Primary Examiner, Art Unit 2871 8/21/2026
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