DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-18 and 21-22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhang et al. (US 2024/0005858).
Regarding claim 1, Zhang discloses an array substrate (fig. 16, para. 0145), comprising:
a substrate (01, fig. 21);
a plurality of pixel driving circuits (20), located at a side of the substrate, and arranged in multiple rows and multiple columns (array of pixel circuit 20, fig. 16); a pixel driving circuit(such as fig. 12) of the plurality of pixel driving circuits comprises a compensation transistor (M0), a driving transistor (MT) and a first conductive connection portion (N1), wherein a control electrode of the driving transistor (MT) and a second electrode of the compensation transistor (M0) are both electrically connected to the first conductive connection portion (N1) (paras. 0097-0098);
a plurality of first scanning signal lines (S1), located at a side of the substrate, wherein the plurality of first scanning signal lines are extended along a row direction and are sequentially arranged along a column direction, the row direction and the column
direction are parallel to the substrate and cross-arranged (array of pixel circuit 20, fig. 16); a first scanning signal line (S1) of the plurality of first scanning signal lines is electrically connected to control electrodes of compensation transistors (M0) of a row of pixel driving circuits (20);
wherein the first conductive connection portion (N1) and the first scanning signal line (S1) do not overlap in a direction perpendicular to the substrate (fig. 2, para. 0048).
Regarding claim 2, Zhang discloses the pixel driving circuit further comprises: a data writing transistor (M3) and a first light-emitting control transistor (M6), wherein a second electrode of the data writing transistor is electrically connected (at N2) to a first electrode of the driving transistor (MT) and a second electrode of the first light-emitting control transistor (M6) (para. 0086);
the array substrate further comprises: a plurality of second scanning signal lines (S4) and a plurality of light-emitting control signal lines (EM1, EM2), located at a side of the substrate; the plurality of second scanning signal lines (S4) all extend along the row direction and are sequentially arranged along the column direction, and a second scanning signal line (S4) of plurality of second scanning signal lines is electrically connected to control electrodes of data writing transistors (M3) of the row of pixel driving circuits; the plurality of light-emitting control signal lines (EM1, EM2) all extend along the row direction and are sequentially arranged along the column direction, and a light-emitting control signal line (EM2) of the plurality of light-emitting control signal lines is electrically connected to control electrodes of first light-emitting control transistors (M6) of the row of pixel driving circuits;
the array substrate further comprises: a plurality of row pixel regions (fig. 16), wherein the plurality of row pixel regions extend along the row direction and are sequentially disposed along the column direction; the row of pixel driving circuits (20) are disposed within a row pixel region, and a first scanning signal line (S1), a second scanning signal line (S4) and a light-emitting control signal line (EM2) electrically connected to the row of pixel driving circuits are located in the row pixel region where the row of pixel driving circuits are located (paras. 0097-0098 and 0109);
wherein in the row pixel region: an orthographic projection of the first scanning
signal line (S1) on the substrate is located at a side of an orthographic projection of the second scanning signal line (S4) on the substrate away from an orthographic projection of the light-emitting control signal line on the substrate, and an orthographic projection of the driving transistor (MT) on the substrate is located between the orthographic projection of the second scanning signal line (S4) on the substrate and the orthographic projection of the light-emitting control signal line (EM2) on the substrate (paras. 0097-0098 and 0109).
Regarding claim 3, Zhang discloses in the row pixel region, the compensation transistor (M0) and the first conductive connection portion (N1) are sequentially disposed along the column direction; wherein the compensation transistor (M0) passes through the first scanning signal line (S1), and an orthographic projection of the second electrode of the compensation transistor (M0) on the substrate is located at a side of an orthographic projection of the first scanning signal line (S1) on the substrate close to the orthographic projection of the light-emitting control signal line on the substrate, wherein the first conductive connection portion (N1) is located at a side of the first scanning signal line (S1) close to the light-emitting control signal line (EM2) (paras. 0097-0098 and 0109).
Regarding claim 4, Zhang discloses in the row pixel region, a portion of an orthographic projection of the data writing transistor (M3) on the substrate is disposed opposite to an orthographic projection of the compensation transistor (M0) on the substrate in the row direction, and another portion of the orthographic projection of the data writing transistor (M3) on the substrate is disposed opposite to an orthographic projection of the first conductive connection portion (N1) on the substrate in the row direction (paras. 0097-0098 and 0109).
Regarding claim 5, Zhang discloses the data writing transistor (M3) passes through the second scanning signal line (S4), and the data writing transistor (M3) is located at a side of the first scanning signal line (S1) close to the light-emitting control signal line (EM2);
the array substrate further comprises:
a plurality of data transfer portions (data), wherein the plurality of data transfer portions (data) are located at a side of the plurality of pixel driving circuits (20) away from the substrate;
a plurality of data lines ( data voltage signal line data, para. 0074), wherein the plurality of data lines are located at a side of the plurality of data transfer portions (data) away from the substrate, the plurality of data lines extend along the column direction and are sequentially arranged along the row direction, and a data line of the plurality of data lines is electrically connected to first electrodes of data writing transistors (M3) of the row of pixel driving circuits through a data transfer portion (data) of the plurality of data transfer portions (paras. 0097-0098 and 0109);
wherein in the row pixel region, an orthographic projection of the data transfer
portion (data) on the substrate is located between the orthographic projection of the first
scanning signal line (S1) on the substrate and the orthographic projection of the second
scanning signal line (S4) on the substrate (paras. 0097-0098 and 0109).
Regarding claim 6, Zhang discloses in the row pixel region, a portion of an orthographic projection of the first conductive connection portion (N1) on the substrate overlaps with a portion of an orthographic projection of the compensation transistor (M0) on the substrate, and another portion of the orthographic projection of the first conductive connection portion (N1) on the substrate overlaps with a portion of the orthographic projection of the driving transistor (MT) on the substrate (paras. 0097-0098).
Regarding claim 7, Zhang discloses the pixel driving circuit further comprises a second conductive connection portion (N2), wherein the second conductive connection portion is electrically connected to the first electrode of the driving transistor (MT), the second electrode of the first light-emitting control transistor (M6), and a second electrode of the data writing transistor (M3) (paras. 0097-0098);
an orthographic projection of the second conductive connection portion (N2) on the substrate does not overlap with an orthographic projection of the first scanning signal line (S1) on the substrate (paras. 0097-0098).
Regarding claim 8, Zhang discloses the pixel circuit further comprises a third reset transistor (M4), wherein a second electrode of the third reset transistor (M4) is electrically connected to the second conductive connection portion (N2);
the array substrate further comprises: a plurality of second reset signal lines (S3), wherein the plurality of second reset signal lines (S3) are located at a side of the plurality of pixel driving circuits away from the substrate, the plurality of second reset signal lines (S3) all extend along the row direction, and sequentially arrange along the column direction; a second reset signal line (S3) of the plurality of second reset signal lines (S3) is electrically connected to control electrodes of third reset transistors (M4) of the row of pixel driving circuits; the second reset signal line (S3) electrically connected to the row of pixel driving circuits is located in the row pixel region where the row of pixel driving circuits are located;
wherein in the row pixel region, the second reset signal line (S3) is located at a side of the light-emitting control signal line (EM2) away from the first scanning signal line (S1).
Regarding claim 9, Zhang discloses a plurality of third initialization signal lines (Vref), located at a side of the substrate; the plurality of third initialization signal lines (Vref) all extend along the row direction and are sequentially arranged along the column direction, and a third initialization signal line of the plurality of third initialization signal lines (Vref) is electrically connected to first electrodes of third reset transistors (M4) of the row of pixel driving circuits;
in the row pixel region: an orthographic projection of the third initialization signal line (Vref) on the substrate at least partially overlaps with the orthographic projection of the light-emitting control signal line on the substrate (paras. 0097-0099).
Regarding claim 10, Zhang discloses in the row pixel region: the third reset transistor (M4) passes through the second reset signal line (S3) and is located at a side of the third initialization signal line (Vref) away from the light-emitting control signal line; wherein an orthographic projection of a first electrode of the third reset transistor (M4) on the substrate is located between an orthographic projection of the third initialization signal line (Vref) on the substrate and an orthographic projection of the second reset signal line on the substrate, and an orthographic projection of the second electrode of the third reset transistor (M4) on the substrate is located at a side of an orthographic projection of the second reset signal line (S3) on the substrate away from the orthographic projection of the third initialization signal line (Vref) on the substrate;
the second conductive connection portion (N2) crosses over the third initialization signal line (Vref), the light-emitting control signal line (EM2), and the second reset signal line (S3), and is electrically connected to the second electrode of the third reset transistor (M4) (paras. 0097-0099).
Regarding claim 11, Zhang discloses a portion of the orthographic projection of the second conductive connection portion (N2) on the substrate overlaps with an orthographic projection of the second electrode, a control electrode, and a portion of the first electrode of the third reset transistor (M4) on the substrate (paras. 0097-0099).
Regarding claim 12, Zhang discloses the pixel driving circuit further comprises a second light-emitting control transistor (M1) and a second reset transistor (M8); a first electrode of the second light-emitting control transistor (M1) is electrically connected to a second electrode of the driving transistor (MT) and a first electrode of the compensation transistor (M0), and a second electrode of the second light-emitting control transistor (M1) is electrically connected to a light-emitting device (D) and a second electrode of the second reset transistor (M8); wherein control electrodes of second light-emitting control transistors (M1) of the row of pixel driving circuits are electrically connected to the light-emitting control signal line (EM1), and control electrodes of second reset transistors (M8) of the row of pixel driving circuits are electrically connected to the second reset signal line (S3) (paras. 0097-0099);
the array substrate further comprises: a plurality of second initialization signal lines (Vref), wherein the plurality of second initialization signal lines (Vref) are located at a side of the plurality of pixel driving circuits away from the substrate, the plurality of second initialization signal lines (Vref) extend along the row direction, and are sequentially arranged along the column direction; a second initialization signal line (Vref) of the plurality of second initialization signal lines is electrically connected to first electrodes of second reset transistors (M8) of the row of pixel driving circuits (paras. 0097-0099);
wherein in the row pixel region, an orthographic projection of the second initialization signal line (Vref) on the substrate is located at a side of an orthographic projection of the second reset signal line (S3) on the substrate away from the orthographic projection of the first scanning signal line (S1) on the substrate (paras. 0097-0099).
Regarding claim 13, Zhang discloses the pixel driving circuit further comprises: a first reset transistor (M5) and a third conductive connection portion (N3), wherein the third conductive connection portion (N3) is electrically connected to a second electrode of the first reset transistor (M5), the second electrode of the driving transistor (MT) and the first electrode of the compensation transistor (M0);
the array substrate further comprises: a plurality of first reset signal lines (S6), wherein the plurality of first reset signal lines (S6) are located at a side of the plurality of pixel driving circuits away from the substrate; the plurality of first reset signal lines (S6) all extend along the row direction and are sequentially arranged along the column direction, and a first reset signal line (S6) of the plurality of first reset signal lines is electrically connected to control electrodes of first reset transistors (M5) of the row of pixel driving circuits;
wherein in the row pixel region, an orthographic projection of the first reset signal line (S6) on the substrate is located at a side of an orthographic projection of the light-emitting control signal line (EM1) on the substrate away from the orthographic projection of the first scanning signal line on the substrate (paras. 0097-0099).
Regarding claim 14, Zhang discloses a plurality of first initialization signal lines (Vref), located at a side of the plurality of pixel driving circuits away from the substrate, wherein the plurality of first initialization signal lines (Vref) all extend along the row direction and are sequentially arranged along the column direction, and a first initialization signal line of the plurality of first initialization signal lines is electrically connected to first electrodes of first reset transistors (M5) of the row of pixel driving circuits;
wherein in the row pixel region, the first initialization signal line (Vref) is located at a side of the first reset signal line (S6) away from the first scanning signal line (S1) (paras. 0097-0099).
Regarding claim 15, Zhang discloses the first reset transistor (M5) passes through the first reset signal line (S6), an orthographic projection of a first electrode of the first reset transistor (M5) on the substrate is located between the orthographic projection of the first reset signal line (S6) on the substrate and an orthographic projection of the first initialization signal line (Vref) on the substrate, and an orthographic projection of the second electrode of the first reset transistor (M5) on the substrate is located between the orthographic projection of the first reset signal line (S6) on the substrate and the orthographic projection of the second reset signal line (S3) on the substrate (paras. 0097-0099).
Regarding claim 16, Zhang discloses the orthogonal projection of the first reset signal line (S6) on the substrate overlaps with the orthogonal projection of the second initialization signal line (Vref) on the substrate (paras. 0097-0099).
Regarding claim 17, Zhang discloses a plurality of auxiliary signal lines (PVDD, PVEE), located at a side of the substrate, wherein the plurality of auxiliary signal lines (PVDD, PVEE) all extend along the column direction and are sequentially arranged along the row direction (para. 0101);
wherein an auxiliary signal line (PVDD) of the plurality of auxiliary signal lines is electrically connected to any one of the first initialization signal line (Vref), the second initialization signal line and the third initialization signal line (para. 0101).
Regarding claim 18, Zhang discloses the row of pixel driving circuits is divided into a plurality of repeating units (such as 20, fig. 16) sequentially disposed along the row direction, wherein a repeating unit of the plurality of repeating units comprises at least one of the row of pixel driving circuits;
the auxiliary signal line is located between two adjacent repeating units in the row direction (para. 0101).
Regarding claim 21, Zhang discloses a display panel (160, fig. 16), comprising: the array substrate; a light-emitting device layer, located at a side of the array substrate away from the substrate, and an encapsulation layer, located at a side of the light-emitting device layer away from the array substrate (para. 0145).
Regarding claim 22, Zhang discloses a driving chip (1601), electrically connect to the display panel (para. 0109).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ke (US 2023/0215314) discloses a display panel also includes a reset signal line, an initialization signal line. The reset signal line is configured to provide a reset signal to a gate of the driving transistor, the initialization signal line is configured to provide an initialization signal to the light-emitting element (fig. 1, para. 0005).
Xu et al. (US 2023/0076760) disclose the display panel includes a pixel circuit, a light-emitting element, and a signal line group including at least one signal line for providing control signals or input signals for transistors in the pixel circuit (fig. 1, para. 0005).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER T NGUYEN whose telephone number is (571)272-7696. The examiner can normally be reached Mon-Fri 7:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at 5712722963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JENNIFER T NGUYEN/ Primary Examiner, Art Unit 2629
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