Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed 1/17/2025 in which Claims 1-14 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 5-7, 10-11, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chinese Patent Publication CN 110189697 to Wu (relied on English Translation) in view of U.S. Patent Publication 2022/0293038 to Zhao et al (“Zhao”).
As to Claim 1, Wu teaches a pixel circuit, comprising a light-emitting element, a first energy storage circuit, a second energy storage circuit, a third energy storage circuit, a driving circuit, a data writing circuit, a transfer control circuit, and a first setting circuit (the reference signal input module 104 includes a first transistor T1 [first setting circuit], see ¶ 0050; the storage capacitor control module 105 includes a second transistor T2 [transfer control circuit], a first capacitor C1 [first energy storage circuit], a second capacitor C2 [third energy storage circuit] and a third capacitor C3 [second energy storage circuit], see ¶ 0051; the data signal input module 102 includes a third transistor T3 [data writing circuit], see ¶ 0052; the light emitting module 101 includes a driving transistor DT and light-emitting device D, see ¶ 0054; Fig. 2);
the first energy storage circuit is electrically connected to a first node (the second terminal of the first capacitor C1 [first energy storage circuit] is electrically connected to the second node b [first node], see ¶ 0051); the second energy storage circuit is electrically connected to a second node and a third node (the second terminal of the first capacitor C1 [second energy storage circuit] is electrically connected to the first node a [second node], and the second terminal of the third capacitor C3 is electrically connected to the third node c [third node], see ¶ 0051); the third energy storage circuit is electrically connected to a second terminal of the first energy storage circuit and the third node (the second terminal of the second capacitor C2 [third energy storage circuit] is electrically connected to the third node c, see ¶ 0051; Figure 2 illustrates capacitor C2 [third energy storage circuit] connected to the second terminal of the first capacitor C1 [first energy storage circuit]); the first energy storage circuit, the second energy storage circuit, and the third energy storage circuit are configured to store electrical energy (a first capacitor C1 [first energy storage circuit], a second capacitor C2 [third energy storage circuit] and a third capacitor C3 [second energy storage circuit], see ¶ 0051);
a control terminal of the driving circuit is electrically connected to the second node (gate of the driving transistor DT is electrically connected to the first node a [second node], see ¶ 0054), a first terminal of the driving circuit is electrically connected to the first voltage terminal (the source of the driving transistor DT is electrically connected to the first power supply signal VDD, see ¶ 0054), and a second terminal of the driving circuit is electrically connected to the light-emitting element through the third node (the drain of the driving transistor DT is electrically connected to the third node c, see ¶ 0054), the driving circuit is configured to generate a driving current to drive the light-emitting element under a control of potential of the second node (the threshold voltage sensing module 103 electrically connected with the third node c, a light emitting module 101 is electrically connected to the first node and a third node c, see ¶ 0008; gate of the driving transistor DT is electrically connected to the first node a [second node], see ¶ 0054);
the data writing circuit is electrically connected to a writing control terminal, a data line, and the first node, and is configured to write a data voltage provided by the data line to the first node under a control of a writing control signal provided by the writing control terminal (data signal input module 102 [data writing circuit] is connected to the second control signal S2 [writing control signal] and the data signal Data [data line], and is used to output the data signal Data to the second node b [first node] under the control of the second control signal S2, see ¶ 0049);
the transfer control circuit is electrically connected to a first scanning terminal, the first node, and the second node, and is configured to control the connection between the first node and the second node under a control of a first scanning signal provided by the first scanning terminal (storage capacitor control module 105 includes a second transistor T2…the gate of the second transistor T2 is electrically connected to the third control signal S3 [first scanning signal], the source of the second transistor T2 is electrically connected to the first node a [second node], and the drain of the second transistor T2 is electrically connected to the second node b [first node], see ¶ 0051);
the first setting circuit is electrically connected to a second scanning terminal, the second node, and a setting voltage terminal, and is configured to write a setting voltage provided by the setting voltage terminal to the second node under a control of a second scanning signal provided by the second scanning terminal (the reference signal input module 104 [first setting circuit] includes a first transistor T1. The gate of the first transistor T1 is electrically connected to the first control signal S1 [second scanning signal], the source of the first transistor T1 is electrically connected to the data signal Data, and the drain of the first transistor T1 is electrically connected to the first node a [second node], see ¶ 0050).
Wu teaches the first energy storage circuit is electrically connected to a DC voltage terminal.
Zhao teaches the first energy storage circuit is electrically connected to a DC voltage terminal (the second terminal of the second energy storage circuit 20 is electrically coupled to a DC voltage terminal, see ¶ 0066, Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Wu with Zhao to teach the first energy storage circuit is electrically connected to a DC voltage terminal. The suggestion/motivation would have been in order for the second energy storage circuit to stably maintain the potential of the second node C (see ¶ 0066).
As to Claim 2, Wu and Zhao depending from Claim 1, Wu teaches a first light emitting control circuit; the first light emitting control circuit is electrically connected to a first light emitting control terminal, the third node, and a first electrode of the light-emitting element, and is configured to control the connection between the third node and the first electrode of the light-emitting element under a control of a first light emitting control signal provided by the first light emitting control terminal (the gate of the fourth transistor T4 is connected to the fourth control signal S4 [first light-emitting control signa;], source electrode of fourth transistor T4 is electrically connected to the voltage detecting module 106, the drain of the fourth transistor T4 is electrically connected to the third node c, the voltage detection module 106 is used to output an initial voltage to the first node a and to calculate the initial threshold voltage by detecting the voltage of the third node c, see ¶ 0053; The anode of the light-emitting device D [first electrode of the light-emitting element] is electrically connected to the third node c, see ¶ 0054);
a second electrode of the light-emitting element is electrically connected to the second voltage terminal (the cathode of the light-emitting device D is electrically connected to the second power supply signal VSS, see ¶ 0054).
As to Claim 5, Wu and Zhao depending from Claim 1, Wu teaches wherein the first energy storage circuit comprises a first capacitor, the second energy storage circuit comprises a second capacitor, and the third energy storage circuit comprises a third capacitor (a first capacitor C1 [first energy storage circuit], a second capacitor C2 [third energy storage circuit] and a third capacitor C3 [second energy storage circuit], see ¶ 0051);
a first terminal of the second capacitor is electrically connected to the second node, and a second terminal of the second capacitor is electrically connected to the third node (the first terminal of the third capacitor C3 [second capacitor] is electrically connected to the first node a [second node], the second terminal of the third capacitor C3 is electrically connected to the third node c [third node], see ¶ 0051; a first terminal of the third capacitor is electrically connected to the second terminal of the first capacitor, and a second terminal of the third capacitor is electrically connected to the third node (The first terminal of the second capacitor C2 [third capacitor] is electrically connected to the second node b, and the second terminal of the second capacitor C2 is electrically connected to the third node c [third node], see ¶ 0051. Figure 2 illustrates capacitor C2 connected to the second terminal of capacitor C1 [first capacitor]).
Zhao teaches a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the DC voltage terminal (the first terminal of the second energy storage circuit 20 is connected to a node, the second terminal of the second energy storage circuit 20 is electrically coupled to a DC voltage terminal, see ¶ 0066, Fig. 2).
As to Claim 6, Wu and Zhao depending from Claim 1, Wu teaches wherein the data writing circuit comprises a first transistor, and the transfer control circuit comprises a second transistor; a gate of the first transistor is electrically connected to the writing control terminal, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the first node (The gate of the third transistor T3 is electrically connected to the second control signal S2 [writing control terminal], the source of the third transistor T3 is electrically connected to the data signal Data, and the drain of the third transistor T3 is electrically connected to the second node b [first node], see ¶ 0052); a gate of the second transistor is electrically connected to the first scanning terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node (The gate of the second transistor T2 is electrically connected to the third control signal S3 [first scanning signal], the source of the second transistor T2 is electrically connected to the first node a [second ode], and the drain of the second transistor T2 is electrically connected to the second node b [first node], see ¶ 0051).
As to Claim 7, Wu and Zhao depending from Claim 1, Wu teaches wherein the first setting circuit comprises a third transistor; a gate of the third transistor is electrically connected to the second scanning terminal, a first electrode of the third transistor is electrically connected to the setting voltage terminal, and a second electrode of the third transistor is electrically connected to the second node (The gate of the first transistor T1 is electrically connected to the first control signal S1 [second scanning terminal], the source of the first transistor T1 is electrically connected to the data signal Data, and the drain of the first transistor T1 is electrically connected to the first node a [second node], see ¶ 0050).
As to Claim 10, Wu and Zhao depending from Claim 1, Wu teaches
a driving method, applied to the pixel circuit wherein a display period of the pixel circuit comprises a compensation stage, a data transfer stage, and a light emitting stage set sequentially, the light emitting stage comprises a data writing period (The real-time threshold voltage processing stage includes a second initialization stage t3 [data transfer stage], a real-time threshold voltage acquisition stage t4 [compensation stage], a compensation stage t5 [data writing period], and an emission stage t6 [light emitting stage], see ¶ 0060);
the driving method comprises: in the compensation stage, the first setting circuit writes the setting voltage provided by the setting voltage terminal to the second node under the control of the second scanning signal, the first voltage signal provided by the first voltage terminal charges each energy storage circuit through the driving circuit to change the potential of the third node until the driving circuit is disconnected (During the real-time threshold voltage detection stage t4, the first control signal S1 [second scanning signal] is at a high potential…The compensated reference signal Ref [setting voltage terminal] continues to be output to the first node a. Due to the effects of the first capacitor C1, the second capacitor C2, and the third capacitor C3, the potentials of the second node b and the third node c [third node] change accordingly until the driving transistor DT is turned off, see ¶ 0060);
in the data transfer stage, the transfer control circuit controls the connection between the first node and the second node under the control of the first scanning signal (During the second initialization phase t3, the first control signal S1, the third control signal S3 [first scanning signal], and the fourth control signal S4 are all at high potentials, the second control signal S2 is at a low potential, the potential vini+Vth of the compensated reference signal Ref is output to the first node a and the second node b, see ¶ 0060);
in the light emitting stage, the driving circuit drives the light-emitting element to emit light (During the light-emitting stage, the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are all at low potentials, and the light emitting module 101 emits light, see ¶ 0060);
during the data writing period, the data writing circuit writes the data voltage provided by the data line to the first node under the control of the writing control signal (During the compensation phase t5, the second control signal S2 [writing control signal] is at a high potential, while the first control signal S1, the third control signal S3, and the fourth control signal S4 are all at a low potential. The potential change of the second node b corresponds to the potential of the compensated data signal Data, see ¶ 0060).
As to Claim 11, Wu and Zhao depending from Claim 1, Wu teaches wherein the pixel circuit further comprises a first light emitting control circuit; the driving method further comprises: in the light emitting stage, the first light emitting control circuit controls the connection between the third node and the first electrode of the light-emitting element under the control of the first light emitting control signal (In the sensing phase t2, the first control signal S1 and the fourth control signal S4 [light emitting control signal] are both at high potentials, the second control signal S2 and the third control signal S3 are both at low potentials, the voltage detection module 106 detects the voltage of the third node c, and calculates the initial threshold voltage Vth, see ¶ 0059; During the second initialization phase t3, the first control signal S1, the third control signal S3, and the fourth control signal S4 are all at high potentials, the second control signal S2 is at a low potential, the potential vini+Vth of the compensated reference signal Ref is output to the first node a and the second node b, and the compensated initial voltage is output to the third node c….During the light-emitting stage, the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are all at low potentials, and the light emitting module 101 emits light, see ¶ 0060).
As to Claim 14, Wu and Zhao depending from Claim 1, Wu teaches a display device comprising the pixel circuit (a pixel driving circuit and a display panel, see ¶ 0002).
Claim(s) 3, 4, 8, 9, 12, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chinese Patent Publication CN 110189697 to Wu (relied on English Translation) in view of U.S. Patent Publication 2022/0293038 to Zhao et al (“Zhao”) in further view of U.S. Patent Publication 2022/0309990 to Qiu et al (“Qiu”).
As to Claim 3, Wu and Zhao depending from Claim 1, Wu and Zhao do not expressly disclose further comprising a second setting circuit; the second setting circuit is electrically connected to a third scanning terminal and a third voltage terminal, the second setting circuit is further electrically connected to the second node or the third node, the second setting circuit is configured to write a third voltage signal provided by the third voltage terminal into the second node or the third node under a control of a third scanning signal provided by the third scanning terminal. Qiu teaches further comprising a second setting circuit; the second setting circuit is electrically connected to a third scanning terminal and a third voltage terminal, the second setting circuit is further electrically connected to the second node or the third node (a first electrode may be connected with the first initial power source terminal Vinit 1, and a second electrode may be connected with the second node N2, see ¶ 0080; A gate of the compensating transistor T3 may be connected with the gate signal terminal G1 [third scanning terminal], a first electrode may be connected with the third node N3 [third node], and a second electrode may be connected with the second node N2, see ¶ 0081. Figure 6 illustrates transistor T3 is connected to power source terminal Vinit1 via second node N2),
the second setting circuit is configured to write a third voltage signal provided by the third voltage terminal into the second node or the third node under a control of a third scanning signal provided by the third scanning terminal (a first electrode may be connected with the first initial power source terminal Vinit 1, see ¶ 0080; A gate of the compensating transistor T3 may be connected with the gate signal terminal G1 [third scanning terminal], a first electrode may be connected with the third node N3 [third node], and a second electrode may be connected with the second node N2, see ¶ 0081. Figure 6 illustrates transistor T3 is connected to power source terminal Vinit1 via second node N2).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Wu and Zhao with Qiu to teach a second setting circuit; the second setting circuit is electrically connected to a third scanning terminal and a third voltage terminal, the second setting circuit is further electrically connected to the second node or the third node, the second setting circuit is configured to write a third voltage signal provided by the third voltage terminal into the second node or the third node under a control of a third scanning signal provided by the third scanning terminal. The suggestion/motivation would have been in order for the first pixel circuit outputs a driving signal to the first light-emitting element connected with the first pixel circuit in response to a first initial power source signal provided by a first initial power source terminal in a light-emitting phase (see ¶ 0115).
As to Claim 4, Wu and Zhao depending from Claim 2, Wu and Zhao do not expressly disclose further comprising a second light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal through the second light emitting control circuit; the second light emitting control circuit is electrically connected to a second light emitting control terminal, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under a control of a second light emitting control signal provided by the second light emitting control terminal.
Qiu teaches further comprising a second light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal through the second light emitting control circuit; the second light emitting control circuit is electrically connected to a second light emitting control terminal, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under a control of a second light emitting control signal provided by the second light emitting control terminal (Both a gate of the first light-emitting control transistor T4 and a gate of the second light-emitting control transistor T5 are connected with the light-emitting control signal terminal EM [second light emitting control terminal], a first electrode of the first light-emitting control transistor T4 is connected with the direct current signal terminal VDD [first voltage terminal] and a second electrode of the first light-emitting control transistor T4 is connected with the first node N1, see ¶ 0082; A gate of the driving transistor T6 may be connected with the second node N2, a first electrode of the driving transistor T6 may be connected with the first node N1 [first terminal of the driving circuit under control of a second light emitting control signal] and a second electrode of the driving transistor T6 may be connected with the third node N3, see ¶ 0084. Figure 6 illustrates transistor T4 connected between the first voltage terminal VDD and the first node under control of an emission signal).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Wu and Zhao with Qiu to teach a second light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal through the second light emitting control circuit; the second light emitting control circuit is electrically connected to a second light emitting control terminal, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under a control of a second light emitting control signal provided by the second light emitting control terminal. The suggestion/motivation would have been in order for the light-emitting control unit may be connected with the light-emitting control signal terminal, the direct current signal terminal, the first node the third node, and the target node respectively, and may be configured to control an on-off state of the direct current signal terminal and the first node as well as an on-off state of the third node and the target node in response to the light-emitting control signal (see ¶ 0072).
As to Claim 8, Wu, Zhao and Qiu depending from Claim 3, Qiu teaches wherein the second setting circuit comprises a fourth transistor; a gate of the fourth transistor is electrically connected to the third scanning terminal, a first electrode of the fourth transistor is electrically connected to the third voltage terminal, and a second electrode of the fourth transistor is electrically connected to the second node or the third node (a first electrode may be connected with the first initial power source terminal Vinit 1, and a second electrode may be connected with the second node N2, see ¶ 0080; A gate of the compensating transistor T3 may be connected with the gate signal terminal G1 [third scanning terminal], a first electrode may be connected with the third node N3 [third node], and a second electrode may be connected with the second node N2, see ¶ 0081. Figure 6 illustrates transistor T3 is connected to power source terminal Vinit1 via second node N2).
As to Claim 9, Wu, Zhao and Qiu depending from Claim 4, Qiu teaches wherein the driving circuit comprises a driving transistor, the second light emitting control circuit comprises a fifth transistor, and the first light emitting control circuit comprises a sixth transistor (Both a gate of the first light-emitting control transistor T4 [fifth transistor] and a gate of the second light-emitting control transistor T5 [sixth transistor] are connected with the light-emitting control signal terminal EM, see ¶ 0082);
a gate of the driving transistor is electrically connected to the second node, and a second electrode of the driving transistor is electrically connected to the third node (A gate of the driving transistor T6 may be connected with the second node N2 [second node], a first electrode of the driving transistor T6 may be connected with the first node N1 and a second electrode of the driving transistor T6 may be connected with the third node N3 [third node], see ¶ 0084);
a gate of the fifth transistor is electrically connected to the second light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor (Both a gate of the first light-emitting control transistor T4 and a gate of the second light-emitting control transistor T5 are connected with the light-emitting control signal terminal EM [second light emitting control terminal], a first electrode of the first light-emitting control transistor T4 is connected with the direct current signal terminal VDD [first voltage terminal] and a second electrode of the first light-emitting control transistor T4 is connected with the first node N1, see ¶ 0082. Figure 6 illustrates node N1 connected to a first electrode of a driving transistor);
a gate of the sixth transistor is electrically connected to the first light emitting control terminal, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element (Both a gate of the first light-emitting control transistor T4 and a gate of the second light-emitting control transistor T5 are connected with the light-emitting control signal terminal EM [second light emitting control terminal], a first electrode of the second light-emitting control transistor T5 is connected with the third node N3 [third node] and a second electrode of the second light-emitting control transistor T5 is connected with the target node N01, see ¶ 0082. Figure 6 illustrates node N01 connected to a first electrode of the light emitting element).
As to Claim 12, Wu, Zhao and Qiu depending from Claim 10, Qiu teaches wherein the pixel circuit further comprises a second setting circuit; the display period further comprises an initialization stage set before the compensation stage;
the driving method further comprises: in the initialization stage, the second setting circuit writes the third voltage signal into the second node or the third node under the control of the third scanning signal (In the pull-down phase t1, the potential of the pull-down control signal provided by the pull-down control terminal RST 2 is the first potential. At this time, the pull-down transistor 2 may be turned on. The first initial power source terminal Vinit 1 may output the first initial power source signal at the second potential to the second node N2 through the pull-down transistor 2 to achieve pull-down reset of the second node N2, see ¶ 0121, Figure 6 illustrates a transistor T3 [second setting circuit] writes the initial voltage Vinit1 into the third node under control of scanning signal G1).
As to Claim 13, Wu, Zhao and Qiu depending from Claim 10, Qiu teaches
wherein the pixel circuit further comprises a second light emitting control circuit; the driving method further comprises: in the compensation stage and the light emitting stage, the second light emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the second light emitting control signal (In the light-emitting phase t3, the potential of the light-emitting control signal provided by the light-emitting control signal terminal EM [second light emitting control signal] is the first potential. At this time, the light-emitting control transistors T4 and T5 are both turned on. The direct current signal terminal VDD [first voltage terminal] may output the direct current power source signal to the first node N1 through the light-emitting control transistor T4 [second light emitting control circuit]. The driving transistor T6 may output a driving current to the third node N3 based on the potential of the first node N1 and the potential of the second node N2, see ¶ 0123. Figure 6 illustrates that transistor T4 controls the connection between the direct current signal terminal VDD and the first node N1 to output a power source signal to the first node N1, i.e. the first terminal of the driving transistor T6, under the control of the light-emitting control signal EM).
Conclusion
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/EBONI N GILES/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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