DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 16 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chao (USPN 10,848,063).
With respect to claim 1, Chao discloses, in Fig. 2, a gate drive circuit (Fig. 2 lest 104, 106, M1 and M2) for a power inverter leg in a power inverter (M1 with M2 power inverter is merely intended use of the leg of M1 with M2), the power inverter leg comprising a first power switch (M1) with a first reverse conduction channel (M1 having a reverse or negative current flow, i.e., negative with respect to typical positive current flow of VIN to VOUT/SW, as detected by 223) and a second power switch (M2) with a second reverse conduction channel (M2 have a reversed, e.g., positive, current flow, i.e., positive is reversed form the typical negative current flow of VOUT/SW to ground, as detected by 224), the power inverter leg being configured to drive an inductive-resistive load (104 with 106. Inductor 104 is a wound coil/wire which will inherently have at least some resistance. Furthermore, 104 has an inductance and thus may be interpreted as an inductive-resistive load), the gate drive circuit comprising:
a first gate drive sub-circuit (335 of Fig. 3 with one of 331 and 332, see Figs. 4A and 4B) for controlling switching of the first power switch (via the control under hg);
a second gate drive sub-circuit (336 of Fig. 3 with one of 331 and 332, see Fig. 4A and 4B) for controlling switching of the second power switch (via the control under lg); wherein
the gate drive circuit is configured to control switching of the first and second power switches in a complementary manner (M1 and M2 are complementary controlled), and based on gate drive control signals of the first and second gate drive sub-circuits (based on hg and lg), the gate drive control signals being indicative of conduction conditions of the first and second reverse conduction channels (as controlled/determined by I_NEG and I_POS of 223 and 224) and a slope of load current in the inductive-resistive load (slope of the load current is detected by 225, since 225 detects if the direction of the current is a positive, i.e., slope increasing, see Col. 5 lines 37-41, or negative, i.e., slope decreasing, Col. 5 lines 52-56).
With respect to claim 16, a power inverter (power inverter is merely intended use of the circuit) comprising a gate drive (Fig. 2 lest M1, M2 104 and 106) a power inverter leg of the power inverter (M1 with M2), the power inverter leg comprising a first power switch (M1) with a first reverse conduction channel (M1 having a reverse or negative current flow, i.e., negative with respect to typical positive current flow of VIN to VOUT/SW, as detected by 223) and a second power switch (M2) with a second reverse conduction channel (M2 have a reversed, e.g., positive, current flow, i.e., positive is reversed form the typical negative current flow of VOUT/SW to ground, as detected by 224), the power inverter leg being configured to drive an inductive-resistive load (104 with 106. Inductor 104 is a wound coil/wire which will inherently have at least some resistance. Furthermore, 104 has an inductance and thus may be interpreted as an inductive-resistive load), the gate drive circuit comprising:
a first gate drive sub-circuit (335 of Fig. 3 with one of 331 and 332, see Figs. 4A and 4B) for controlling switching of the first power switch (via the control under hg);
a second gate drive sub-circuit (336 of Fig. 3 with one of 331 and 332, see Fig. 4A and 4B) for controlling switching of the second power switch (via the control under lg); wherein
the gate drive circuit is configured to control switching of the first and second power switches in a complementary manner (M1 and M2 are complementary controlled), and based on gate drive control signals of the first and second gate drive sub-circuits (based on hg and lg), the gate drive control signals being indicative of conduction conditions of the first and second reverse conduction channels (as controlled/determined by I_NEG and I_POS of 223 and 224) and a slope of load current in the inductive-resistive load (slope of the load current is detected by 225, since 225 detects if the direction of the current is a positive, i.e., slope increasing, see Col. 5 lines 37-41, or negative, i.e., slope decreasing, Col. 5 lines 52-56).
Claim 17 merely discloses the method of operating/constructing the circuit as recited in claim 1. Thus, claim 17 is rejected for essentially the same reasons as claim 1.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lisuwandi (USPN 9,305,700)
With respect to claim 16, Lisuwandi discloses, in Figs. 15-16, a power inverter (Fig. 15 operation details disclosed in Figs. 15 and 16) comprising a gate drive (Fig. 15 lest SW-A, SW-B, C and L1) a power inverter leg of the power inverter (SW-A with SW-B), the power inverter leg comprising a first power switch (SW-A) with a first reverse conduction channel (SW-A having a reverse current flow through the body diode between SW and Vs) and a second power switch (SW-B) with a second reverse conduction channel (having a reverse current flow through the body diode between SW and ground), the power inverter leg being configured to drive an inductive-resistive load (C with L1. Inductor L1 is a wound coil/wire which will inherently have at least some resistance. Furthermore, L1 has an inductance and thus may be interpreted as an inductive-resistive load), the gate drive circuit comprising:
a first gate drive sub-circuit (44) for controlling switching of the first power switch (44 supplying the gate control of SW-A);
a second gate drive sub-circuit (29) for controlling switching of the second power switch (29 providing the gate control of SW-B); wherein
the gate drive circuit is configured to control switching of the first and second power switches in a complementary manner (SW-A is on when SW-B is off and vice versa, see Col. 7 line 67 to Col. 8 line 8), and based on gate drive control signals of the first and second gate drive sub-circuits (based on output of 44 and 29), the gate drive control signals being indicative of conduction conditions of the first and second reverse conduction channels (as controlled/determined by 24 and 26 which will determine the forward and/or reverse conduction of the switch channels via detecting the voltages across the first and second power switches) and a slope of load current in the inductive-resistive load (the gate drive circuit further controls the switching of the gate drive circuitry according to the slope of the inductive-resistive load current, since SW-B is opened and SW-A is turned on via the reset when the slope of the load current is increasing in a positive direction above ground/zero, see Col. 8 lines 15-19 and Fig. 16).
Claim 17 merely discloses the method of operating/constructing the circuit as recited in claim 1. Thus, claim 17 is rejected for essentially the same reasons as claim 1.
Allowable Subject Matter
Claims 2-15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claims 2-15, the cited prior art, and more specifically Ikeda et al. (USPAPN 2013/0002227), fails to disclose the gate drive circuit “configured:
to generate a first gate drive control signal indicative of the conductive condition of the first reverse conduction channel;
to generate a second gate drive control signal indicative of the slope of load current in the inductive-resistive load; and
to switch the first power switch to a conductive state when the first reverse conduction channel is in a conductive condition and when the slope of load current in the inductive-resistive load is positive (Examiner’s emphasis).
Ikeda fails to disclose the first gate drive control signal that is indicated of the reverse conduction channel, the second gate drive signals that is indicative of the slope of the load and the switching of the first power switch to a conductive when the first reverse conduction channel is conductive and when the slope of the load current is positive. Furthermore, it is noted that when a positive slope current flows through CS1/the resistive-inductive load of Ikeda FET1b/S1b is conductive, see paragraph 0036. Moreover, S1b/FET1b is conductive the reverse conduction path of (D1b) is shorted and thus the conduction path of D1b is blocked/non-conductive. Thus, Ikeda fails to disclose the operation of to switch the first power switch to a conductive state when the first reverse conduction channel is in a conductive condition and when the slope of load current in the inductive-resistive load is positive, since both FET1b/S1b and D1b are not both conductive when the slope of the load current is positive.
Cited Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Teng et al. (USPAPN 2009/0174485) discloses, in Fig. 3, a power leg including a first and second transistor (112 with 114) for generating an AC output signal (output on 120) and a resistive-inductive load (116). The circuit of Fig. 2 including a gate drive circuit (Fig. 3 lest 112, 114, 116 and 118) for providing gate control signals to each of the transistors (outputs of 104) according to the reverse conduction of the transistors of the power leg (as determined 106a and 106b) and the slope of the load current (rising as determined by 106a and falling as determined by 106b).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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