Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Figs. 5, 28 and 29 in the reply filed on 12/29/2025 is acknowledged. The traversal is on the ground(s) that it should be no undue burden on the Examiner to consider all claims in the single application. This is not found persuasive because each specie defined in the election/restriction requires a separate classification and different field of search. For example, Fig. 5 (Species 1) and Fig. 7 (Species 2) have two different pixel structure that would operate differently based on the inputs provided by the shift registers. Further, Species 3-10 specify different and exclusive shift register structures and output signals that would interact differently with the pixel structures in Figs. 5 and 7. Each permutation would require different search strings and considerations. There would be a serious search in examination burden on the examiner if restriction is not required. The requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 8, 10, 15, 16, and 18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 5, 6, 10, 10 (for latter limitation of claim 16 in current application) and 13 of copending Application No. 18/294,003 (Yu et al – PGPUB 2025/0078740 A1) In view of Yi et al (PGPUB 2018/0151139 A1).
Current Application – Claim 1
18/294,003 – Claim 1
A driving circuit, comprising a driving signal generating circuit,
A driving circuitry, comprising a driving signal generation circuitry,
M output driving terminals and M control circuits;
an m-th control circuit comprises an m-th gating circuit, an m-th output control circuit and an m-th output circuit;
a gating circuitry, an output control circuitry, and an output circuitry,
M is a positive integer; m is a positive integer less than or equal to M;
the driving signal generating circuit is electrically connected to a control clock signal terminal, an (N-1)-th level driving signal output terminal and an N-th level driving signal output terminal, and is configured to perform a shift operation on the (N-1)-th level driving signal provided by the (N-1)-th level driving signal output terminal under a control of a control clock
signal provided by the control clock signal terminal, to obtain and output an N-th level driving signal through the N-th level driving signal output terminal;
wherein the driving signal generation circuitry is electrically coupled to an (N−1)th-level driving signal output end and an Nth-level driving signal output end, and configured to perform a shifting operation on an (N−1)th-level driving signal from the (N−1)th-level driving signal output end to obtain and output an Nth-level driving signal through the Nth-level driving signal output end;
the m-th gating circuit is electrically connected to an m-th first node, an m-th gating input terminal and an m-th gating control terminal, and is configured to control a writing of the m-th gating input signal provided by the m-th gating input terminal into the m-th first node under the control of the m-th gating control signal provided by the m-th gating control terminal;
the gating circuitry is electrically coupled to a first node, a gating input end, and a gating control end, and configured to write a gating input signal from the gating input end into the first node under the control of a gating control signal from the gating control end;
a first terminal of the m-th output control circuit is electrically connected to the N-th level driving signal output end, and
a first end of the output control circuitry is electrically coupled to the Nth-level driving signal output end, and
the second end of the m-th output control circuit is electrically connected to the m-th first node, and
a second end of the output control circuitry is electrically coupled to the first node, and
… is configured to perform a NAND operation on the N-th level driving signal and a potential of a second end of the m-th output control circuit to obtain an m-th first output signal; and
the output control circuitry is configured to perform an NAND operation on the Nth-level driving signal and a potential at the second end of the output control circuitry to obtain a first output signal; and
the m-th output circuit is configured to invert the m-th first output signal, and obtain an m-th output driving signal through the m-th output driving terminal;
the output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end,
N is a positive integer.
where N is a positive integer.
Copending Yu reference teaches most of the limitations required by current application’s claim 1 except for “M” or “m-th” limitations and “M is a positive integer; m is a positive integer less than or equal to M”. Yu reference only uses “a” phrase for each limitation and does not necessarily teach the integer requirement.
Yi (PGPUB 2018/0151139 A1) – Yi(Fig. 8) teaches a plurality of stage GOA units with N output driving terminals. Further, Yi teaches at least N-1 set of GOA unit circuit as shown in Fig. 1 is comprised in the embodiment in Fig. 8.
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Yi’s display driver structure into Yu’s display device, so as to reduce clock signal loading and lower RC delay and power consumption (¶ 13).
Dependent claims 8, 10, 15, 16 and 18 of current application corresponds to 5, 6, 10, 10 and 13 respectively.
Allowable Subject Matter
Claims 2, 4, 9, 12, 17, 19 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant’s invention regards the scan driver circuitry for LED / OLED pixel. The scan driver circuitry performs NAND operation on the N-the driving signal and a potential of output control circuit to generate the output signal. Applicant specifically claims the limitations, “a driving circuit comprising a driving signal generating circuit, M output driving terminals and M control circuits; … the driving signal generating circuit is electrically connected to a clock signal terminal, an (N-1)-th level driving signal output terminal and an N-th level driving signal output terminal, and is configured to perform a shift operation on the (N-1)-th level driving signal … under a control of a control clock signal … to obtain an output an N-th level driving signal … a first terminal of the m-th output control circuit is electrically connected to the N-th level driving signal output end, and the second end of the m-th output control circuit is electrically connected to the m-th first node, and is configured to perform a NAND operation on the N-th level driving signal and a potential of a second end of the m-th output control circuit to obtain an m-th first output signal”.
Examiner conducted a search to find a prior art that would teach the limitations above alone or in combination. However, none of the prior arts specifically teach the limitations. Followings are the most relevant prior arts from the search.
Wang (PGPUB 2020/0380931) – Wang teaches a shift register circuit for display device with NAND gate but does not specifically teach all of the limitations discussed above.
Xing et al (PGPUB 2019/0325801 A1) – Xing teaches a shift register circuit for display with NAND gate signal processing module 50 as shown in Fig. 5. However, Xing does not specifically teach all of the limitations discussed above.
Tao et al (PGPUB 2019/0206504 A1) – Tao teaches a shift register circuit for display with NAND gate signal in output control circuit 30 as shown in Figs. 1 and 4. However, Tao does not specifically teach all of the limitations discussed above.
Yi et al (PGPUB 2018/0151139 A1) – Yi teaches a shift register circuit for display with NAND gate 4 in Fig. 3. However, Yi does not specifically teach all of the limitations discussed above.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623
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