DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to amendments/remarks for application 18996785 filed on 06/05/2026 Claims 1-3, 6-8, 11-15, 21, 22 and 25-31 are presented for examination.
Prior Art Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6-8, 25, 26, 28, 29 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al. (US Patent Pub. No. 2021/0201805 A1)
Regarding claim 1, Feng teaches a driving circuit (Feng, Fig. 11, shift register), comprising N driving output terminals (Feng, Fig. 11, output signal terminals OP1-OP4), a first node control circuit (Feng, Fig. 11, first transmission circuit 320), a second node control circuit (Feng, Fig. 11, second transmission circuit 330) and a driving output circuit (Feng, sub-units 100 and 200);
the first node control circuit is electrically connected to a first node and is configured to control a potential of the first node (Feng, Fig. 11, first transmission circuit 320 connected to Q1);
the second node control circuit is electrically connected to a second node and is configured to control a potential of the second node (Feng, Fig. 11, second transmission circuit 330 connected to Q2);
the driving output circuit is electrically connected to the first node, the second node and the N driving output terminals, and is configured to control a n-th driving output terminal to output a n-th driving signal under a control of the potential of the first node and the potential of the second node (Feng, Fig. 16, output signals depend on Q1 and Q2; Feng, Fig. 11, sub-unit 100 receives signal QB_A which is output from sub-unit 200, and sub-unit 200 receives signal QB_B which is output from sub-unit 100, hence the output signals from each of the sub-unit would depend on both the signals at Q1 and Q2 directly or indirectly);
N is an integer greater than 1; n is a positive integer less than or equal to N (Feng, Fig. 11, N=4 and n=1-4).
Regarding claim 2, Feng teaches the limitations of claim 1 and further teaches the driving output circuit comprises N driving output units; N is an integer greater than 1 (Feng, Fig. 11, output signal terminals OP1-OP4, N=4);
the n-th driving output unit is electrically connected to the first node, the second node and the n-th driving output terminal, and is configured to control the n-th driving output terminal to output the n-th driving signal under the control of the potential of the first node and the potential of the second node (Feng, Fig. 11, output signal terminals OP1-4 are electronically connected Q1 Q; Feng, Fig. 16, output signals depend on Q1 and Q2);
n is a positive integer less than or equal to N (Feng, Fig. 11, N=4 and n=1-4).
Regarding claim 6, Feng teaches the limitations of claim 1 and further teaches a first energy storage circuit; wherein
a first terminal of the first energy storage circuit is electrically connected to the first node, a second terminal of the first energy storage circuit is electrically connected to one of the N driving output terminals, and the first energy storage circuit is configured to store electrical energy (Feng, Fig. 12A, capacitor C2 connected to Q1 and OP1);
wherein the first energy storage circuit comprises a first capacitor;
a first electrode plate of the first capacitor is electrically connected to the first node, and the second electrode plate of the first capacitor is electrically connected to one of the N driving output terminals (Feng, Fig. 12A, capacitor C2 connected to Q1 and OP1).
Regarding claim 7, Feng teaches the limitations of claim 1 and further teaches at least two first energy storage circuits (Feng, Fig. 12A, capacitors C2 and C4);
first terminals of the at least two first energy storage circuits are electrically connected to the first node, second terminals of the at least two first energy storage circuits are electrically connected to at least two of the driving output terminals, and the first energy storage circuits are configured to store electrical energy (Feng, Fig. 12A, capacitors C2 and C4 are connected between Q1 and OP1 and OP3 respectively).
Regarding claim 8, Feng teaches the limitations of claim 1 and further teaches a second energy storage circuit (Feng, Fig. 12B);
the second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is configured to store electrical energy (Feng, Fig. 12B, capacitor C3 connected to Q2).
Regarding claim 25, Feng teaches the limitations of claim 7 and further teaches the driving circuit comprises N first energy storage circuits, and the n-th first energy storage circuit comprises an n-th first capacitor (Feng, Figs. 12A and 12B, each output comprises its own corresponding capacitor);
the n-th first capacitor is electrically connected to the first node, and the second electrode plate of the n-th first capacitor is electrically connected to the n-th driving output terminal (Feng, Fig. 12A, e.g., capacitor C2 connected to Q1 and OP1).
Regarding claim 26, Feng teaches the limitations of claim 8 and further teaches the second energy storage circuit comprises a second capacitor;
a first electrode plate of the second capacitor is electrically connected to the second node, and the second electrode plate of the second capacitor is electrically connected to the second terminal of one of N output reset circuits (Feng, Fig. 12B, C3 connected to Q2 and OP2, which is connected to M23 and M25 which outputs QB_A, Feng, Fig. 11, fourth reset circuit 250 outputs QB_A).
Regarding claim 28, Feng teaches the limitations of claim 1 and further teaches a driving method, applied to the driving circuit according to claim 1,comprising:
a first node control circuit controlling a potential of the first node (Feng, Fig. 11, first transmission circuit 320);
a second node control circuit controlling a potential of the second node (Feng, Fig. 11, second transmission circuit 330);
a driving output circuit (Feng, sub-units 100 and 200) controlling a n-th driving output terminal to output the n-th driving signal under the control of the potential of the first node and the potential of the second node (Feng, Fig. 16, output signals depend on Q1 and Q2);
wherein N is an integer greater than 1; n is a positive integer less than or equal to N (Feng, Fig. 11, N=4 and n=1-4).
Regarding claim 29, Feng teaches the limitations of claim 1 and further teaches a display substrate comprising the driving circuit according to claim 1 (Feng, Fig. 17, display device 1 with display panel 10).
Regarding claim 31, Feng teaches the limitations of claim 28 and further teaches a display device comprising the driving circuit according to claim 28 (Feng, Fig. 17, display device 1).
Response to Arguments
Applicant's arguments filed on 06/05/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., driving circuit sharing by multiple rows of pixel circuits, thereby increasing vertical space, reducing horizontal space, and saving border) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Furthermore, Feng still teaches the argued limitation that Applicant alleged Feng does not teach. It is clearly shown in Fig. 11 of Feng that sub-unit 100 receives signal QB_A which is output from sub-unit 200, and sub-unit 200 receives signal QB_B which is output from sub-unit 100, hence the output signals from each of the sub-unit would depend on both the signals at Q1 and Q2 directly or indirectly.
In light of the above, the rejections are maintained.
Allowable Subject Matter
Claims 3, 11-15, 21, 22, 27 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3, 11 and 27, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the connection of the reset circuit and the output circuits together in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Regarding claim 12, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the connection of the output reset transistor in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Regarding claims 13-15, 21 and 22, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, configurations and the interconnections of the third node control circuit and the carry output circuit in the manner claimed as a whole in the respective claims, is not sufficiently taught or suggested in the prior art.
Regarding claim 30, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the configuration and interconnection of the second capacitor and the N-1 pseudo capacitors in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG HUI LIANG whose telephone number is (571)272-0487. The examiner can normally be reached M-F 7am-3pm EST.
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/DONG HUI LIANG/Primary Examiner, Art Unit 2629
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