DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to application 18996785 filed on 01/17/2025 Claims 1-3, 6-8, 11-15, 21, 22 and 25-31 are presented for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy of foreign priority document, Application No. CN202310466808.8, filed in China on 04/26/2023, has been received.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 13, 14 and 26 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 13 recites the limitations "the first clock signal terminal" in lines 2-3; “the first clock signal” in line 5. There are insufficient antecedent bases for these limitations in the claim.
Claim 14 recites the limitations "the first clock signal terminal, the input terminal, the third node, the fourth voltage terminal, the fifth voltage terminal and the reset terminal" in lines 3-4; “the first clock signal” in lines 5-6; “the reset signal” in line 8. There is insufficient antecedent bases for these limitations in the claim.
Claim 26 recites the limitation "the N output reset circuits" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Prior Art Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6-8, 25, 28, 29 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al. (US Patent Pub. No. 2021/0201805 A1)
Regarding claim 1, Feng teaches a driving circuit (Feng, Fig. 11, shift register), comprising N driving output terminals (Feng, Fig. 11, output signal terminals OP1-OP4), a first node control circuit (Feng, Fig. 11, first transmission circuit 320), a second node control circuit (Feng, Fig. 11, second transmission circuit 330) and a driving output circuit (Feng, sub-units 100 and 200);
the first node control circuit is electrically connected to a first node and is configured to control a potential of the first node (Feng, Fig. 11, first transmission circuit 320 connected to Q1);
the second node control circuit is electrically connected to a second node and is configured to control a potential of the second node (Feng, Fig. 11, second transmission circuit 330 connected to Q2);
the driving output circuit is electrically connected to the first node, the second node and the N driving output terminals, and is configured to control a n-th driving output terminal to output a n-th driving signal under a control of the potential of the first node and the potential of the second node (Feng, Fig. 16, output signals depend on Q1 and Q2);
N is an integer greater than 1; n is a positive integer less than or equal to N (Feng, Fig. 11, N=4 and n=1-4).
Regarding claim 2, Feng teaches the limitations of claim 1 and further teaches the driving output circuit comprises N driving output units; N is an integer greater than 1 (Feng, Fig. 11, output signal terminals OP1-OP4, N=4);
the n-th driving output unit is electrically connected to the first node, the second node and the n-th driving output terminal, and is configured to control the n-th driving output terminal to output the n-th driving signal under the control of the potential of the first node and the potential of the second node (Feng, Fig. 11, output signal terminals OP1-4 are electronically connected Q1 Q; Feng, Fig. 16, output signals depend on Q1 and Q2);
n is a positive integer less than or equal to N (Feng, Fig. 11, N=4 and n=1-4).
Regarding claim 6, Feng teaches the limitations of claim 1 and further teaches a first energy storage circuit; wherein
a first terminal of the first energy storage circuit is electrically connected to the first node, a second terminal of the first energy storage circuit is electrically connected to one of the N driving output terminals, and the first energy storage circuit is configured to store electrical energy (Feng, Fig. 12A, capacitor C2 connected to Q1 and OP1);
wherein the first energy storage circuit comprises a first capacitor;
a first electrode plate of the first capacitor is electrically connected to the first node, and the second electrode plate of the first capacitor is electrically connected to one of the N driving output terminals (Feng, Fig. 12A, capacitor C2 connected to Q1 and OP1).
Regarding claim 7, Feng teaches the limitations of claim 1 and further teaches at least two first energy storage circuits (Feng, Fig. 12A, capacitors C2 and C4);
first terminals of the at least two first energy storage circuits are electrically connected to the first node, second terminals of the at least two first energy storage circuits are electrically connected to at least two of the driving output terminals, and the first energy storage circuits are configured to store electrical energy (Feng, Fig. 12A, capacitors C2 and C4 are connected between Q1 and OP1 and OP3 respectively).
Regarding claim 8, Feng teaches the limitations of claim 1 and further teaches a second energy storage circuit (Feng, Fig. 12B);
the second energy storage circuit is electrically connected to the second node, and the second energy storage circuit is configured to store electrical energy (Feng, Fig. 12B, capacitor C3 connected to Q2).
Regarding claim 25, Feng teaches the limitations of claim 7 and further teaches the driving circuit comprises N first energy storage circuits, and the n-th first energy storage circuit comprises an n-th first capacitor (Feng, Figs. 12A and 12B, each output comprises its own corresponding capacitor);
the n-th first capacitor is electrically connected to the first node, and the second electrode plate of the n-th first capacitor is electrically connected to the n-th driving output terminal (Feng, Fig. 12A, e.g., capacitor C2 connected to Q1 and OP1).
Regarding claim 28, Feng teaches the limitations of claim 1 and further teaches a driving method, applied to the driving circuit according to claim 1,comprising:
a first node control circuit controlling a potential of the first node (Feng, Fig. 11, first transmission circuit 320);
a second node control circuit controlling a potential of the second node (Feng, Fig. 11, second transmission circuit 330);
a driving output circuit (Feng, sub-units 100 and 200) controlling a n-th driving output terminal to output the n-th driving signal under the control of the potential of the first node and the potential of the second node (Feng, Fig. 16, output signals depend on Q1 and Q2);
wherein N is an integer greater than 1; n is a positive integer less than or equal to N (Feng, Fig. 11, N=4 and n=1-4).
Regarding claim 29, Feng teaches the limitations of claim 1 and further teaches a display substrate comprising the driving circuit according to claim 1 (Feng, Fig. 17, display device 1 with display panel 10).
Regarding claim 31, Feng teaches the limitations of claim 28 and further teaches a display device comprising the driving circuit according to claim 28 (Feng, Fig. 17, display device 1).
Allowable Subject Matter
Claims 3, 11, 12, 15, 21, 22, 27 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3, 11 and 27, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the connection of the reset circuit and the output circuits together in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Regarding claim 12, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the connection of the output reset transistor in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Regarding claim 15, 21 and 22, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, configurations and the interconnections of the third node control circuit and the carry output circuit in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Regarding claim 30, the prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the configuration and interconnection of the second capacitor and the N-1 pseudo capacitors in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
U.S. Patent Publication No. 2005/0206604 A1 to Washio et al. discloses a similar invention as recited, specifically the controlling output with two node control circuits, see Figs. 4 and 5(a).
U.S. Patent Publication No. 2009/0273593 A1 to Tonogai et al. discloses a similar invention as recited, specifically the controlling output with two node control circuits, see Figs. 7 and 8.
U.S. Patent Publication No. 2016/0253977 A1 to Ohkawa et al. discloses a similar invention as recited, specifically the controlling output with two node control circuits, see Figs. 16 and 17.
U.S. Patent Publication No. 2018/0226959 A1 to Su et al. discloses a similar invention as recited, specifically the controlling output with two node control circuits, see Figs. 1-3.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG HUI LIANG whose telephone number is (571)272-0487. The examiner can normally be reached M-F 7am-3pm EST.
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/DONG HUI LIANG/Primary Examiner, Art Unit 2629