DETAILED ACTION
This Office action is in response to the application and preliminary amendment filed on 17 January 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 12, 14 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR 2006 0065441A1 (hereinafter “D1”).
The written opinion of the International Searching Authority issued in the parent application no. PCT/EP2023/069576 and received as part of this National Stage application (available in the application file, dated 17 January 2025) has been fully considered and the Examiner hereby adopts the positions therein with respect to the disposition of claims 1 and 5 as lacking novelty, or in other words being anticipated by, the cited reference. See MPEP § 1893.03(e), subsection II.
Claims 12 and 15 recite substantially similar subject matter as respective claims 1 and 5, in the form of a method rather than device. As such, D1 is considered to anticipate the method claims in the same ways and for the same reasons as for the device claims.
In re claims 4 and 14, D1 discloses wherein the at least one signal plane includes two or more signal planes disposed adjacent to one another (see Fig. 2: adjacent signal planes Sia1, Sia2, etc.).
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent 9,549,467 (hereinafter “D2”).
The written opinion of the International Searching Authority issued in the parent application no. PCT/EP2023/069576 and received as part of this National Stage application (available in the application file, dated 17 January 2025) has been fully considered and the Examiner hereby adopts the positions therein with respect to the disposition of claim 1 as lacking novelty, or in other words being anticipated by, the cited reference. See MPEP § 1893.03(e), subsection II.
Claim 12 recites substantially similar subject matter as respective claim 1, in the form of a method rather than device. As such, D2 is considered to anticipate the method claim in the same ways and for the same reasons as for the device claim.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP 2006 109533 A (hereinafter “D3”).
The written opinion of the International Searching Authority issued in the parent application no. PCT/EP2023/069576 and received as part of this National Stage application (available in the application file, dated 17 January 2025) has been fully considered and the Examiner hereby adopts the positions therein with respect to the disposition of claim 1 as lacking novelty, or in other words being anticipated by, the cited reference. See MPEP § 1893.03(e), subsection II.
Claim 12 recites substantially similar subject matter as respective claim 1, in the form of a method rather than device. As such, D3 is considered to anticipate the method claim in the same ways and for the same reasons as for the device claim.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by EP 3 624 324 A1 (hereinafter “D4”).
The written opinion of the International Searching Authority issued in the parent application no. PCT/EP2023/069576 and received as part of this National Stage application (available in the application file, dated 17 January 2025) has been fully considered and the Examiner hereby adopts the positions therein with respect to the disposition of claim 1 as lacking novelty, or in other words being anticipated by, the cited reference. See MPEP § 1893.03(e), subsection II.
Claim 12 recites substantially similar subject matter as respective claim 1, in the form of a method rather than device. As such, D4 is considered to anticipate the method claim in the same ways and for the same reasons as for the device claim.
Claim(s) 6-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo et al. (US Patent 10,802,518; hereinafter “Luo”).
In re claim 6, Luo discloses a multi-phase power converter (Figs. 1A, 3) comprising:
a printed circuit board (100, 300); and
a power converter phase (100, 100A) including:
a first bridge leg including a first high-side transistor (Fig. 1A: 107) and a first low-side transistor (Fig. 1A: 108), the first high-side transistor configured to selectively conduit current between a positive terminal of an input bus (VIN) and a first intermediate node (SW), and the first low-side transistor configured to selectively conduit current between the first intermediate node (SW) and a negative terminal of the input bus (PGND);
a first driver circuit (Fig. 1A: 106) disposed adjacent to the first bridge leg and configured to generate drive signals for controlling operation of each of the first high-side transistor and the first low-side transistor (as understood from the term “driver”, it’s function is to drive the gates of HS and LS FETs with appropriate control signals; see also col. 6: 7-58); and
a plurality of other power components (Fig. 3: 304A-N, output capacitor (unlabeled)) disposed adjacent to the first bridge leg (Fig. 3: within 100A) and opposite from the first driver circuit (c.f. Figs. 1A and 3), the plurality of other power components connected to the first intermediate node for receiving power therefrom (as shown in Fig. 3; col. 5: 64 – col. 6: 6).
In re claim 7, Luo discloses (see citations above with respect to claim 6; Luo discloses an additional bridge leg as 100B in Fig. 3, comprising the same IC shown in Fig. 1A; see col. 7: 22-29; therefore the citations provided above likewise apply, mutatis mutandis, to claim 7) wherein the power converter phase further includes: a second bridge leg including a second high-side transistor and a second low-side transistor, the second high-side transistor configured to selectively conduit current between the positive terminal of the input bus and a second intermediate node, and the second low-side transistor configured to selectively conduit current between the second intermediate node and the negative terminal of the input bus; and a second driver circuit disposed adjacent to the second bridge leg and configured to generate drive signals for controlling the operation of each of the second high-side transistor and the second low-side transistor, wherein the plurality of other power components is disposed adjacent to the second bridge leg and opposite from the second driver circuit, the plurality of other power components connected to the second intermediate node for receiving power therefrom.
In re claim 8, Luo discloses wherein the power converter phase is one of a plurality of power converter phases each disposed on the printed circuit board (see Fig. 3: 100A-100N).
In re claim 9, Luo discloses wherein the plurality of power converter phases each include corresponding switching transistors arranged in a straight line (see Fig. 3: 100A-100).
In re claim 10, Luo discloses wherein the plurality of power converter phases each include corresponding driver circuits arranged on a same side of the straight line of the switching transistors (see Figs. 1A: driver 106, transistors 107, 108; c.f. Fig. 3: 100A-100N).
In re claim 11, Luo discloses wherein the first bridge leg is one of a plurality of sets of switching transistors each defining a corresponding bridge leg (Fig. 3: 100A-100N); and a local decoupling capacitor located between each set of set of switching transistors and configured to supply high-frequency currents thereto (Fig. 1A: capacitor 109; see col. 4: 19-21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D3.
The written opinion of the International Searching Authority issued in the parent application no. PCT/EP2023/069576 and received as part of this National Stage application (available in the application file, dated 17 January 2025), has been fully considered and the Examiner hereby adopts the positions therein with respect to the disposition of claim 2 as lacking an inventive step, or in other words being obvious over, the cited references. See MPEP § 1893.03(e), subsection II.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of Luo.
In re claim 16, D1 discloses the invention according to claim 1 as explained above, but does not further disclose a power converter phase, wherein the power converter phase includes: a first bridge leg including a first high-side transistor and a first low-side transistor, the first high-side transistor configured to selectively conduit current between a positive terminal of an input bus and a first intermediate node, and the first low-side transistor configured to selectively conduit current between the first intermediate node and a negative terminal of the input bus; a first driver circuit disposed adjacent to the first bridge leg and configured to generate drive signals for controlling operation of each of the first high-side transistor and the first low-side transistor; and a plurality of other power components disposed adjacent to the first bridge leg and opposite from the first driver circuit, the plurality of other power components connected to the first intermediate node for receiving power therefrom.
Whereas Luo discloses a multi-phase power converter (Figs. 1A, 3) comprising:
a printed circuit board (100, 300); and
a power converter phase (100, 100A) including:
a first bridge leg including a first high-side transistor (Fig. 1A: 107) and a first low-side transistor (Fig. 1A: 108), the first high-side transistor configured to selectively conduit current between a positive terminal of an input bus (VIN) and a first intermediate node (SW), and the first low-side transistor configured to selectively conduit current between the first intermediate node (SW) and a negative terminal of the input bus (PGND);
a first driver circuit (Fig. 1A: 106) disposed adjacent to the first bridge leg and configured to generate drive signals for controlling operation of each of the first high-side transistor and the first low-side transistor (as understood from the term “driver”, it’s function is to drive the gates of HS and LS FETs with appropriate control signals; see also col. 6: 7-58); and
a plurality of other power components (Fig. 3: 304A-N, output capacitor (unlabeled)) disposed adjacent to the first bridge leg (Fig. 3: within 100A) and opposite from the first driver circuit (c.f. Figs. 1A and 3), the plurality of other power components connected to the first intermediate node for receiving power therefrom (as shown in Fig. 3; col. 5: 64 – col. 6: 6).
Luo’s layout provides for vertical integration to produce high density, low-noise voltage regulators (Abstract).
Therefore it would have been obvious to one of ordinary skill in the art to modify the converter of D1 according to the vertical integration layout of Luo as cited above in order to produce a high-density and low-noise conversion/regulation system as taught by Luo.
In re claim 17, Luo additionally discloses (see citations above with respect to claim 6; Luo discloses an additional bridge leg as 100B in Fig. 3, comprising the same IC shown in Fig. 1A; see col. 7: 22-29; therefore the citations provided above likewise apply, mutatis mutandis, to claim 7) wherein the power converter phase further includes: a second bridge leg including a second high-side transistor and a second low-side transistor, the second high-side transistor configured to selectively conduit current between the positive terminal of the input bus and a second intermediate node, and the second low-side transistor configured to selectively conduit current between the second intermediate node and the negative terminal of the input bus; and a second driver circuit disposed adjacent to the second bridge leg and configured to generate drive signals for controlling the operation of each of the second high-side transistor and the second low-side transistor, wherein the plurality of other power components is disposed adjacent to the second bridge leg and opposite from the second driver circuit, the plurality of other power components connected to the second intermediate node for receiving power therefrom.
It would have been obvious to one of ordinary skill in the art to modify the converter of D1 according to the vertical integration layout of Luo, including the second bridge leg as cited above in order to produce the high-density and low-noise conversion/regulation system as taught by Luo.
In re claim 18, the above combination of D1 and Luo would further provide that the power converter phase is one of a plurality of power converter phases each disposed on the printed circuit board (see Luo, Fig. 3: 100A-100N) and wherein the plurality of power converter phases each include corresponding switching transistors arranged in a straight line (see Luo, Fig. 3: 100A-100).
In re claim 19, the above combination of D1 and Luo would further provide that the plurality of power converter phases each include corresponding driver circuits arranged on a same side of the straight line of the switching transistors (see Luo, Fig. 1A: driver 106, transistors 107, 108; c.f. Fig. 3: 100A-100N).
In re claim 20, the above combination of D1 and Luo would further provide that wherein the first bridge leg is one of a plurality of sets of switching transistors each defining a corresponding bridge leg (Luo, Fig. 3: 100A-100N); and a local decoupling capacitor located between each set of set of switching transistors and configured to supply high-frequency currents thereto (Luo, Fig. 1A: capacitor 109; see col. 4: 19-21).
Allowable Subject Matter
Claims 3 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, the closest prior art is D1, disclosing the invention according to claim 1 as explained above. However, D1 does not further disclose wherein the at least one signal plane includes a power area configured to conduct substantially higher current than the signals for controlling operation of the plurality of switching transistors. Further, the additional prior art on record neither discloses nor suggests the features recited in claim 3.
Claim 13 recites substantially similar limitations as claim 3 in the form of a method rather than an apparatus, and claim 13 would thus be allowable for the same reasons as explained above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Patent 6,611,419 discloses an Electronic Assembly Comprising Substrate With Embedded Capacitors.
US 2018/0048255 discloses a HALF-BRIDGE SWITCHING CIRCUIT SYSTEM including a PCB with interleaved positive and negative power planes and with signal planes above or below said power planes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FRED E FINCH III/Primary Examiner, Art Unit 2838
1 Cited by Applicant in the 17 January 2005 Information Disclosure Statement. However, as no English translation of the document was received by the Office, the prior art reference is also cited with the present Office action, and a copy of the original document along with an English machine translation are provided.
Prosecution Insights