D DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-2 and 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2021/0226068 A1, hereinafter referred as “Xie”) in view of Striakhilev et al. (US 2011/0272695 A1, hereinafter referred as “Striakhilev”).
Regarding claim 1, Xie discloses an array substrate, comprising: a base substrate (¶0066 discloses layer of conductive layer is deposited on the substrate 11);
a first electrode layer, disposed on a side of the base substrate, the first electrode layer comprising a first electrode (¶0065-¶0067 disclose depositing the conductive layer on the substrate 11 and patterning the first conducting layer to form a gate electrode 12);
a first conductive layer is, disposed on a side of the first electrode layer away from the base substrate, wherein the first conductive layer comprises a source electrode and a drain electrode, a first gap is provided between the source electrode and the drain electrode (¶0068-¶0071 disclose gate insulation over gate 12 followed by conductive layer 14 pattern into a source/drain electrode; Fig. 4 illustrates separated source and drain portions above the first electrode), and an orthographic projection of the drain electrode on the base substrate is overlapped with an orthographic projection of the first electrode layer on the base substrate (Fig. 4 illustrates an orthographic projection of the source/drain electrodes 14’ is overlapped with an orthographic projection of the gate electrode 12 on substrate 11);
an organic planarization layer (15), comprising a plurality of organic planarization portions arranged at intervals (Fig. 6 illustrates the organic planarization portions 151, 152, and 153 that are distinct and spaced apart by source/drain conductive structures), wherein one organic planarization portion is arranged at least in the first gap (Fig. 6 and ¶0078 disclose first portion 151 is disposed between the source electrode and the drain electrode), at least ends of the source electrode and the drain electrode away from the first gap are not covered by the organic planarization portion (Fig. 6 and ¶0078 disclose portion of the source drain electrode 14′ (the middle raised portion in the figure) is exposed and facilitate connection with an active layer)…; and
an organic active layer (16), disposed on a side of the organic planarization layer (15) away from the base substrate (11) (Fig. 7 and ¶0081 disclose active layer 16 is formed on the upper surface of the etched planarization layer 15 and the source drain electrode 14′), and the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planarization portion away from the first gap (Fig. 7 and ¶0079 discloses the adhesion between the active layer 16 and the second conducting layer 14 is enhanced by the planarization layer 15).
Xie doesn’t disclose an angle between a side wall of the organic planarization portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a side wall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer.
However, in the same field of endeavor, Striakhilev discloses an angle between a side wall of the organic planarization portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a side wall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer (¶0035 discloses TFT structures having nearly vertical or sharp-angled sidewalls; ¶0036-¶0040 disclose photosensitive BCB planarization that smooths those profiles and produces a sidewall angle of about 10 degrees).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Xie in order to smoothen a TFT substrate profile to such an extent that will make it suitable for subsequent fabrication of the OLEDs (¶0008).
Regarding claim 2, Xie discloses the array substrate according to claim 1, wherein a distance between a surface of the organic planarization portion away from the base substrate and the base substrate is greater than or equal to a distance between a surface of the first conductive layer away from the base substrate and the base substrate (Figs. 5-6 and ¶0078 disclose the planarization portions are flush with the top portions of the source/drain electrodes).
Regarding claim 4, Xie doesn’t disclose the array substrate according to claim 1, wherein the angle between the side wall of the organic planarization portion close to the first gap and the surface of the first conductive layer close to the organic planarization layer is less than or equal to 70°.
However, in the same field of endeavor, Striakhilev discloses wherein the angle between the side wall of the organic planarization portion close to the first gap and the surface of the first conductive layer close to the organic planarization layer is less than or equal to 70° (¶0036-¶0040 disclose photosensitive BCB planarization that smooths those profiles and produces a sidewall angle of about 10 degrees).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Xie in order to smoothen a TFT substrate profile to such an extent that will make it suitable for subsequent fabrication of the OLEDs (¶0008).
Regarding claim 5, Xie discloses the array substrate according to claim 1, wherein a distance between a surface of the organic planarization portion away from the base substrate and the first conductive layer is smaller than a thickness of the first conductive layer in a third direction, wherein the third direction is perpendicular to a surface of the base substrate close to the first electrode layer (Fig. 5 illustrates the thickness of the planarization layer 15 is smaller than the thickness of the conductive layer 14).
4. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Striakhilev and in further view of Yoo et al. (US 2016/0227623 A1, hereinafter referred as “Yoo”).
Regarding claim 6, Xie as modified doesn’t disclose the array substrate according to claim 1, wherein a surface of the organic planarization portion away from the base substrate is connected to a side wall of the organic planarization portion via a curved surface.
However, in the same field of endeavor, Yoo discloses wherein a surface of the organic planarization portion away from the base substrate is connected to a side wall of the organic planarization portion via a curved surface (¶0104 discloses the remaining portion of the patterned photoresist layer PR is deformed into a convex and rounded shape through the reflow process).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Xie in order to smoothen a TFT substrate profile to such an extent that will make it suitable for subsequent fabrication of the OLEDs (¶0008).
5. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Striakhilev and in further view of Noh et al. (US 2011/0006290 A1, hereinafter referred as “Noh”).
Regarding claim 8, Xie as modified doesn’t disclose the array substrate according to claim 1, wherein the array substrate further comprises: a gate insulating layer group, disposed on a side of the organic active layer away from the base substrate, and an orthographic projection of the gate insulating layer group on the base substrate is coincided with an orthographic projection of the organic active layer on the base substrate; and a gate layer, disposed on a side of the gate insulating layer group away from the base substrate, wherein the gate layer comprises a gate, and an orthographic projection of the gate on the base substrate is coincided with the orthographic projection of the organic active layer on the base substrate.
However, in the same field of endeavor, Noh discloses wherein the array substrate further comprises: a gate insulating layer group, disposed on a side of the organic active layer away from the base substrate (Fig. 6C and ¶0060 disclose a gate insulating material layer 124 is formed on the organic semiconductor material layer 120), and an orthographic projection of the gate insulating layer group on the base substrate is coincided with an orthographic projection of the organic active layer on the base substrate (Fig. 6D and ¶0061-¶0065 disclose the gate electrode 133, the gate insulating layer 125, and the organic semiconductor layer 121 have substantially the same shape and area in plane view); and a gate layer, disposed on a side of the gate insulating layer group away from the base substrate (¶0047 discloses gate electrode 133 is disposed on the gate insulating layer 125), wherein the gate layer comprises a gate, and an orthographic projection of the gate on the base substrate is coincided with the orthographic projection of the organic active layer on the base substrate (Fig. 6D and ¶0061-¶0065 disclose the gate electrode 133, the gate insulating layer 125, and the organic semiconductor layer 121 have substantially the same shape and area in plane view).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Xie in order to simplify pattern registration and avoid misalignment among the organic semiconductor gate dielectric and the gate.
6. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Striakhilev, in further view of Noh and still in further view of Ohta (US 2010/0237326 A1, hereinafter referred as “Ohta”).
Regarding claim 9, Xie as modified doesn’t disclose the array substrate according to claim 8, wherein the gate insulating layer group comprises: a first gate insulating layer, disposed on the side of the organic active layer away from the base substrate; and a second gate insulating layer, disposed on a side of the first gate insulating layer away from the base substrate, and the second gate insulating layer has a stronger barrier performance to an etching liquid of the gate layer than the first gate insulating layer.
However, in the same field of endeavor, Ohta discloses wherein the gate insulating layer group comprises: a first gate insulating layer (3a), disposed on the side of the organic active layer (6) away from the base substrate (1) (Fig. 3 and ¶0023 disclose organic insulating layer 3a formed over organic semiconductor layer 6, and organic semiconductor layer 6 formed over substrate 1); and a second gate insulating layer (3b), disposed on a side of the first gate insulating layer (3a) away from the base substrate (1) (Fig. 3 and ¶0018 disclose an organic insulating layer containing an insulating organic material 3a and a barrier layer 3b covering the surface of the organic insulating layer 3a), and the second gate insulating layer (3b) has a stronger barrier performance to an etching liquid of the gate layer than the first gate insulating layer (3a) (¶0020 discloses the gate insulating layer including a polymeric material having a high dielectric constant is less resistant to solvent, the barrier layer having high resistance to solvent can be provided to prevent damage to the polymeric material from a solvent or the like during process).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Xie in order to protect the underlying organic gate dielectric during subsequent electrode fabrication.
7. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Striakhilev and in further view of Kippelen et al. (US 2014/0202517 A1, hereinafter referred as “Kippelen”).
Regarding claim 17, Xie as modified doesn’t disclose the array substrate according to claim 1, wherein a work function of the first conductive layer is greater than 4.5 eV.
However, in the same field of endeavor, Kippelen discloses wherein a work function of the first conductive layer is greater than 4.5 eV (Table 3 reports Au = 5.26 ± 0.06 eV).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Xie in order to match energy levels with p-type semiconductors and block electron injection.
8. Claim(s) 28-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Kim (US 2014/0226112 A1, hereinafter referred as “Kim”) and in further view of Striakhilev.
Regarding claim 28, Xie discloses an array substrate, comprising: a base substrate (¶0066 discloses layer of conductive layer is deposited on the substrate 11);
a first electrode layer, disposed on a side of the base substrate, the first electrode layer comprising a first electrode (¶0065-¶0067 disclose depositing the conductive layer on the substrate 11 and patterning the first conducting layer to form a gate electrode 12);
a first conductive layer is, disposed on a side of the first electrode layer away from the base substrate, wherein the first conductive layer comprises a source electrode and a drain electrode, a first gap is provided between the source electrode and the drain electrode (¶0068-¶0071 disclose gate insulation over gate 12 followed by conductive layer 14 pattern into a source/drain electrode; Fig. 4 illustrates separated source and drain portions above the first electrode), and an orthographic projection of the drain electrode on the base substrate is overlapped with an orthographic projection of the first electrode layer on the base substrate (Fig. 4 illustrates an orthographic projection of the source/drain electrodes 14’ is overlapped with an orthographic projection of the gate electrode 12 on substrate 11);
an organic planarization layer (15), comprising a plurality of organic planarization portions arranged at intervals (Fig. 6 illustrates the organic planarization portions 151, 152, and 153 that are distinct and spaced apart by source/drain conductive structures), wherein one organic planarization portion is arranged at least in the first gap (Fig. 6 and ¶0078 disclose first portion 151 is disposed between the source electrode and the drain electrode), at least ends of the source electrode and the drain electrode away from the first gap are not covered by the organic planarization portion (Fig. 6 and ¶0078 disclose portion of the source drain electrode 14′ (the middle raised portion in the figure) is exposed and facilitate connection with an active layer)…; and
an organic active layer (16), disposed on a side of the organic planarization layer (15) away from the base substrate (11) (Fig. 7 and ¶0081 disclose active layer 16 is formed on the upper surface of the etched planarization layer 15 and the source drain electrode 14′), and the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planarization portion away from the first gap (Fig. 7 and ¶0079 discloses the adhesion between the active layer 16 and the second conducting layer 14 is enhanced by the planarization layer 15).
Xie doesn’t disclose an array substrate; a color filter substrate, disposed opposite to the array substrate; and a liquid crystal layer, disposed between the array substrate and the color filter substrate, an angle between a side wall of the organic planarization portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a side wall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer.
However, in the same field of endeavor, Kim discloses an array substrate (¶0030 discloses first substrate [110] may be referred to as a thin film transistor array substrate); a color filter substrate (¶0030 discloses second substrate 120 may be referred to as a color filter array substrate), disposed opposite to the array substrate (¶0029 discloses a first substrate 110 and a second substrate 120 facing each other); and a liquid crystal layer (130), disposed between the array substrate (110) and the color filter substrate (120) (Figs. 1-8 and ¶0029 disclose liquid crystal layer 130 having liquid crystals aligned in a vertical or parallel direction with respect to the two substrates 110 and 120).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Xie in order to provide the switching elements for controlling the pixels of a liquid crystal display.
Further, in the same field of endeavor, Striakhilev discloses an angle between a side wall of the organic planarization portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a side wall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer (¶0035 discloses TFT structures having nearly vertical or sharp-angled sidewalls; ¶0036-¶0040 disclose photosensitive BCB planarization that smooths those profiles and produces a sidewall angle of about 10 degrees).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Xie in order to smoothen a TFT substrate profile to such an extent that will make it suitable for subsequent fabrication of the OLEDs (¶0008).
Regarding claim 29, Xie doesn’t disclose the display panel according to claim 28, wherein the array substrate is a flexible array substrate, and the color filter substrate is a flexible color filter substrate.
However, in the same field of endeavor, Kim discloses wherein the array substrate is a flexible array substrate, and the color filter substrate is a flexible color filter substrate (Figs. 1-3, ¶0006 and ¶0030 disclose a flexible liquid crystal display panel which has flexible substrates instead of glass substrates of a conventional liquid crystal display panel).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Xie in order to provide a flexible display panel that can conform and bend to a desired curved surface.
Regarding claim 30, Xie discloses a display device (¶0002 discloses present invention relates to field of display technologies), comprising:…wherein the array substrate comprises: a base substrate (¶0066 discloses layer of conductive layer is deposited on the substrate 11);
a first electrode layer, disposed on a side of the base substrate, the first electrode layer comprising a first electrode (¶0065-¶0067 disclose depositing the conductive layer on the substrate 11 and patterning the first conducting layer to form a gate electrode 12);
a first conductive layer is, disposed on a side of the first electrode layer away from the base substrate, wherein the first conductive layer comprises a source electrode and a drain electrode, a first gap is provided between the source electrode and the drain electrode (¶0068-¶0071 disclose gate insulation over gate 12 followed by conductive layer 14 pattern into a source/drain electrode; Fig. 4 illustrates separated source and drain portions above the first electrode), and an orthographic projection of the drain electrode on the base substrate is overlapped with an orthographic projection of the first electrode layer on the base substrate (Fig. 4 illustrates an orthographic projection of the source/drain electrodes 14’ is overlapped with an orthographic projection of the gate electrode 12 on substrate 11);
an organic planarization layer (15), comprising a plurality of organic planarization portions arranged at intervals (Fig. 6 illustrates the organic planarization portions 151, 152, and 153 that are distinct and spaced apart by source/drain conductive structures), wherein one organic planarization portion is arranged at least in the first gap (Fig. 6 and ¶0078 disclose first portion 151 is disposed between the source electrode and the drain electrode), at least ends of the source electrode and the drain electrode away from the first gap are not covered by the organic planarization portion (Fig. 6 and ¶0078 disclose portion of the source drain electrode 14′ (the middle raised portion in the figure) is exposed and facilitate connection with an active layer)…; and
an organic active layer (16), disposed on a side of the organic planarization layer (15) away from the base substrate (11) (Fig. 7 and ¶0081 disclose active layer 16 is formed on the upper surface of the etched planarization layer 15 and the source drain electrode 14′), and the organic active layer is connected to the source electrode and the drain electrode on a side of the organic planarization portion away from the first gap (Fig. 7 and ¶0079 discloses the adhesion between the active layer 16 and the second conducting layer 14 is enhanced by the planarization layer 15).
Xie doesn’t disclose a display panel, wherein the display device is a roll-up display device, a foldable display device or a curved display device, wherein the display panel comprises: an array substrate; a color filter substrate, disposed opposite to the array substrate; and a liquid crystal layer, disposed between the array substrate and the color filter substrate; and an angle between a side wall of the organic planarization portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a side wall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer.
However, in the same field of endeavor, Kim discloses a display panel (abstract), wherein the display device is a roll-up display device, a foldable display device or a curved display device (abstract discloses curved-surface display), wherein the display panel comprises: an array substrate (¶0030 discloses first substrate [110] may be referred to as a thin film transistor array substrate); a color filter substrate (¶0030 discloses second substrate 120 may be referred to as a color filter array substrate), disposed opposite to the array substrate (¶0029 discloses a first substrate 110 and a second substrate 120 facing each other); and a liquid crystal layer (130), disposed between the array substrate (110) and the color filter substrate (120) (Figs. 1-8 and ¶0029 disclose liquid crystal layer 130 having liquid crystals aligned in a vertical or parallel direction with respect to the two substrates 110 and 120).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Xie in order to provide the switching elements for controlling the pixels of a liquid crystal display.
Further, in the same field of endeavor, Striakhilev discloses an angle between a side wall of the organic planarization portion close to the first gap and a surface of the first conductive layer close to the organic planarization layer is smaller than an angle between a side wall of the first conductive layer close to the first gap and a surface of the first electrode layer close to the first conductive layer (¶0035 discloses TFT structures having nearly vertical or sharp-angled sidewalls; ¶0036-¶0040 disclose photosensitive BCB planarization that smooths those profiles and produces a sidewall angle of about 10 degrees).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Xie in order to smoothen a TFT substrate profile to such an extent that will make it suitable for subsequent fabrication of the OLEDs (¶0008).
Allowable Subject Matter
9. Claims 3, 7 and 10-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ghebretinsae, Temesghen can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2626
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