DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on January 17, 2025 and July 15, 2025 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Applicant’s election without traverse of Group II (claims 9-17 and 19-21) in the reply filed on January 15, 2026 is acknowledged.
Claim Objections
Claim 14 is objected to because of the following informalities: Line 15 states “the third conductive portions”, please change to “the third active portions”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (USPGPUB 2021/0359058—hereinafter “Cho”).
As to Claim 9 Cho teaches a display panel (Fig. 1 at 500), wherein the display panel comprises a light-emitting unit (Fig. 2 at OLED) and a pixel driving circuit (Fig. 2 at Sub-pixel circuit) for driving the light-emitting unit, the pixel driving circuit comprises a plurality of driving transistors (Fig. 2 at TR1_1 and TR1_2), a second electrode of each of the plurality of driving transistors is connected to a first electrode of a same light-emitting unit (Fig. 2, note TR1_1 and TR1_2 connected to OLED), and each of the plurality of driving transistors is configured to input a driving current to the light-emitting unit according to a voltage of a gate electrode of each of the plurality of driving transistors (Pg. 4, ¶’s 56-57 and 62);
wherein the display panel further comprises:
a base substrate (Figs. 1 and 11 at 50); and
an active layer (See Fig. 11 and Fig. 3 at 10 and Pg. 6, ¶ 76 and Pg. 10, ¶ 118) at a side of the base substrate, wherein the active layer comprises a plurality of third active portions (Fig. 3 at 60), and the third active portions are used to form channel regions of the plurality of driving transistors (Figs. 3-4 at 100, 150 and 170).
As to Claim 10 Cho teaches that the active layer further comprises an eighth active portion (Fig. 5 at 158) and a ninth active portion (Fig. 5 at 159), and the third active portions in a same pixel driving circuit are connected in parallel between the eighth active portion and the ninth active portion (Fig. 6, note TR1_1 and TR1_2 connected to a and b).
As to Claim 11 Cho teaches that an orthographic projection of the eighth active portion on the base substrate and an orthographic projection of the ninth active portion on the base substrate extend along a second direction (See Figs. 5-6 at 158(a) and 159(b) in direction D1 and D4); wherein orthographic projections of the plurality of third active portions in the same pixel driving circuit on the base substrate are spaced apart along the second direction (See Figs. 5-6 at TR1_1 and TR1_2 along second direction D1 and D4).
As to Claim 12 Cho teaches that the display panel further comprises: a first conductive layer at a side of the active layer away from the base substrate (Pg. 6, ¶ 76 and Pg. 10, ¶ 118), wherein the first conductive layer comprises a first conductive portion (Fig. 6 at 105), an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of each of the third active portions in the same pixel driving circuit on the base substrate (Fig. 6, note 105 in relation to TR1_1 and TR1_2); and wherein at least a partial structure of the first conductive portion is used to form a gate electrode of the driving transistors (Pg. 4, ¶ 56).
As to Claim 13 Cho teaches that the pixel driving circuit further comprises a fourth transistor (Fig. 2 at TR2) and a fifth transistor (Fig. 2 at TR5), a first electrode of the fourth transistor is connected to a data line (TR2 connected to DATA), a second electrode of the fourth transistor is connected to a first electrode of at least one of the driving transistors (TR2 connected to TR1_1 and TR1_2), a first electrode of the fifth transistor is connected to a first power line (TR5 connected to ELVDD), and a second electrode of the fifth transistor is connected to the first electrode of at least one of the driving transistors (TR5 connected to TR1_1 and TR1_2); wherein the active layer further comprises: a fourth active portion connected to an end of the eighth active portion (Figs. 5 and 6, TR2 at c connected to a/158), wherein the fourth active portion is used to form a channel region of the fourth transistor (Fig. 6 at TR2); a fifth active portion connected to the other end of the eighth active portion (Figs. 5 and 6, TR5 at h connected to a/158), wherein the fifth active portion is used to form a channel region of the fifth transistor (Fig. 6 at TR5); wherein the display panel further comprises a first conductive layer, the first conductive layer is located at a side of the active layer away from the base substrate (See Fig. 11 and Fig. 3 at 10 and Pg. 6, ¶ 76 and Pg. 10, ¶ 118), and the first conductive layer comprises: a first gate line (Fig. 6 at 110), wherein an orthographic projection of the first gate line on the base substrate extends along a first direction (D3 to D2) and covers an orthographic projection of the fourth active portion on the base substrate (See Fig. 6 regarding TR2 and 110), a partial structure of the first gate line is used to form a gate electrode of the fourth transistor (See Fig. 6 regarding TR2 and 110 and Pg. 4, ¶ 58 and Pg. 9, ¶ 105), and the first direction intersects the second direction (D3/D2 intersects D1/D4); an enable signal line (Fig. 6 at 120), wherein an orthographic projection of the enable signal line on the base substrate extends along the first direction (D3 to D2) and covers an orthographic projection of the fifth active portion on the base substrate, and a partial structure of the enable signal line is used to form the gate electrode of the fifth transistor (See Fig. 6 regarding TR5 and 120); wherein the orthographic projections of the third active portions on the base substrate are located between the orthographic projection of the first gate line on the base substrate and the orthographic projection of the enable signal line on the base substrate (Fig. 6, third active portions of TR1_1 and TR1_2 are located between 110 and 120).
As to Claim 14 Cho teaches that the pixel driving circuit comprises a plurality of pixel driving sub-circuits (Fig. 1 at 10-40 and Pg. 3, ¶’s 46-48), and orthographic projections of the plurality of pixel driving sub-circuits on the base substrate are distributed in an array along a first direction and/or a second direction (See Fig. 1 at 10-40), and the first direction intersects the second direction (See Fig. 1 at D1-D4); each of the plurality of pixel driving sub-circuits comprises the at least one of the driving transistors (Fig. 2 at TR1_1 and TR1_2), and each of the plurality of pixel driving sub-circuits is connected to a same light-emitting unit (Fig. 2, note TR1_1 and TR1_2 connected to OLED), and each of the plurality of pixel driving sub-circuits is used to provide a driving current to the light-emitting unit (Pg. 4, ¶’s 56-57 and 62); wherein the display panel further comprises: an active layer at a side of the base substrate (See Fig. 11 and Fig. 3 at 10 and Pg. 6, ¶ 76 and Pg. 10, ¶ 118), wherein the active layer comprises a plurality of third active portions (Fig. 3 at 60), and the plurality of third active portions are used to form channel regions of the driving transistors (Figs. 3-4 at 100, 150 and 170); a first conductive layer at a side of the active layer away from the base substrate (Pg. 6, ¶ 76 and Pg. 10, ¶ 118), wherein the first conductive layer comprises a plurality of first conductive portions spaced apart (Fig. 6 at 105), the first conductive portions and the third active portions are arranged correspondingly, and an orthographic projection of one of the first conductive portions on the base substrate covers an orthographic projection of a corresponding third active portion on the base substrate (Fig. 6, note 105 in relation to TR1_1 and TR1_2), and the first conductive portion is to form the gate electrode of at least one of the driving transistors (Pg. 4, ¶ 56).
Allowable Subject Matter
Claims 15-17 and 19-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
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/RODNEY AMADIZ/Primary Examiner, Art Unit 2622