DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/17/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the examiner has considered the information disclosure statement.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 10-13, & 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (Korean Patent Application Publication # KR20130077787).
Regarding Claim 1, Lee discloses a component carrier (i.e. printed circuit board 100), comprising:
a stack comprising at least one electrically insulating layer structure (i.e. double-sided metal laminate 111/base substrate 110, first insulating layer 121, solder resist layer 123) and at least one electrically conductive layer structure (i.e. first circuit layer 113, second circuit layer 140); and
a via (i.e. via 142) at least partially embedded in the stack, wherein the via comprises:
a lower metal-filled part (i.e. parts of seed layer 131 & circuit layer 140 that are part of via 142 & via pad 143), and
an upper metal-filled part (i.e. solder bump 160),
wherein the upper metal-filled part is formed directly on the lower metal-filled part with an interface region in between (i.e. where solder bump 160 contacts via pad 143 & surface treatment layer 150 is optional), and
wherein the interface region is substantially free of metal oxides (i.e. a surface oxide film is removed from via pad 143 & connection pad 141 before solder bump 160 is applied) (Fig. 2-12; Paragraphs 0039-0074).
Regarding Claim 2, Lee discloses that the interface region is configured as a continuous region of space between the lower metal-filled part
Regarding Claim 3, Lee discloses that the via (i.e. via 142) is at least partially embedded in the at least one electrically insulating layer structure (i.e. double-sided metal laminate 111/base substrate 110, first insulating layer 121, solder resist layer 123) of the stack, and
wherein the via comprises at least one undercut (i.e. edge of via pad 143 as shown in the figures) along the stack thickness direction (Fig. 12; Paragraphs 0072-0073)
Regarding Claim 4, Lee discloses that the undercut undercut (i.e. edge of via pad 143 as shown in the figures) is located at the lower metal-filled part (i.e. via pad 143) and/or at the upper metal-filled part (Fig. 12; Paragraphs 0072-0073).
Regarding Claim 5, Lee discloses that a diameter of the undercut (i.e. edge of via pad 143 as shown in the figures) varies along the stack thickness direction (Fig. 12; Paragraphs 0072-0073).
Regarding Claim 6, Lee discloses that the undercut (i.e. edge of via pad 143 as shown in the figures) is arranged at a comparable height in the stack thickness direction as the interface region (Fig. 12; Paragraphs 0072-0073).
Regarding Claim 7, Lee discloses the component carrier according to claim 1, being configured as an integrated circuit (IC) (i.e. semiconductor chip) substrate (Paragraph 0002, 0048, 0063, 0071).
Regarding Claim 8, Lee discloses that the at least one electrically insulating layer structure comprises a solder resist layer structure (Fig. 12; Paragraph 0039, 0046-0047, 0062-0064, 0066-0067).
Regarding Claim 9, Lee discloses a method of manufacturing a component carrier (i.e. printed circuit board 100), the method comprising:
forming a stack comprising at least one electrically insulating layer structure (i.e. double-sided metal laminate 111/base substrate 110, first insulating layer 121, solder resist layer 123) and at least one electrically conductive layer structure (i.e. first circuit layer 113, second circuit layer 140);
forming a via hole (i.e. via hole 122 of via 142) at least partially in the stack;
filling a lower part of the via hole with metal
processing the upper surface of the lower metal-filled part by electron attachment (i.e. plasma etching), thereby removing metal oxide (i.e. a surface oxide film is removed from via pad 143 & connection pad 141 before solder bump 160 is applied); and
filling an upper part of the via hole with further metal on the electron attachment processed upper surface of the lower metal-filled part, thereby providing an upper metal-filled part (i.e. solder bump 160) (Fig. 2-12; Paragraphs 0039-0074).
Regarding Claim 10, Lee discloses etching the upper metal surface of the lower metal-filled part (Paragraph 0005, 0045, 0055, 0061, 0064-0068, 0072-0074).
Regarding Claim 12, Lee discloses that the etching forms the metal oxide (i.e. surface oxide film) (Paragraph 0005-0006, 0066, 0072-0074).
Regarding Claim 13, Lee discloses electroless plating the lower metal-filled part (i.e. parts of seed layer 131 & circuit layer 140 that are part of via 142 & via pad 143) subsequently to the electron attachment process (i.e. a surface oxide film is removed from via pad 143 & connection pad 141 by plasma etching before solder bump 160 is applied)to form the upper metal-filled part (i.e. solder bump 160) (Paragraph 0056).
Regarding Claim 17, Lee discloses at least one of the following processing steps:
plasma treatmentThe plasma etching disclosed by Lee can use nitrogen and argon.
Regarding Claim 18, Lee discloses an apparatus for manufacturing a component carrier (i.e. printed circuit board 100), the apparatus comprising:
a drilling unit (i.e. via hole 122 can be formed by a drilling process) configured for forming a via hole (i.e. via hole 122 of via 142) in a stack that comprises at least one electrically insulating layer structure (i.e. double-sided metal laminate 111/base substrate 110, first insulating layer 121, solder resist layer 123) and at least one electrically conductive layer structure(i.e. first circuit layer 113, second circuit layer 140);
a plating unit configured for filling a lower part of the via hole with metal, to provide a lower metal-filled part (i.e. parts of seed layer 131 & circuit layer 140 that are part of via 142 & via pad 143), and filling an upper part of the via hole with further metal on the upper metal surface of the lower metal-filled part, to provide an upper metal-filled part (i.e. solder bump 160); and
an electron attachment unit configured for processing (i.e. plasma etching) the upper surface of the lower metal-filled part by electron attachment (Fig. 2-12; Paragraphs 0039-0074).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Korean Patent Application Publication # KR20130077787) in view of Song et al. (US Patent Application Publication # 2007/0261234).
Regarding Claim 11, Lee does not explicitly disclose that etching comprises using an alkaline etchant.
Song teaches that etching comprises using an alkaline etchant (i.e. alkali chemical cleaning process) (Paragraph 0084).
Song teaches that it is well known in the art of etching to use an alkaline etchant as part of an alkali chemical cleaning process. It would have been obvious to one skilled in the art to use an alkaline etchant in the process of Lee, as taught by Song, in order to maintain a high peel strength.
Claims 14-16 & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Korean Patent Application Publication # KR20130077787) in view of Dong et al. (US Patent Application Publication # 2013/0026921).
Regarding Claim 14, Lee does not explicitly disclose that the method is at least partially performed by a wafer technology-based apparatus.
Dong teaches that the method is at least partially performed by a wafer technology-based apparatus (Abstract; Paragraphs 0004-0007, 0028, 0033, 0035, 0058).
Dong teaches that it is well known in the art to remove metal oxides by using a wafer processing apparatus. It would have been obvious to one skilled in the art to perform the method of Lee using a wafer technology-based apparatus, as taught by Dong, in order to easily, efficiently, and economically remove metal oxides.
Regarding Claim 15, Lee does not explicitly disclose that the electron attachment process is based on negative hydrogen ions as a reducing agent.
Dong teaches that the electron attachment process is based on negative hydrogen ions as a reducing agent (Abstract; Paragraphs 0004-0007, 0028, 0033, 0035, 0042, 0058, 0065, 0067).
Dong teaches that it is well known in the art to remove metal oxides by using a wafer processing apparatus that performs an electron attachment process which uses negatively charged atomic hydrogen ions. Lee also discloses using hydrogen as a reducing gas as part of the plasma etching (Paragraph 0065). It would have been obvious to one skilled in the art to perform the method of Lee using negative hydrogen ions as a reducing agent, as taught by Dong, in order to easily, efficiently, and economically remove metal oxides.
Regarding Claim 16, Lee does not explicitly disclose that the method is free of a sodium peroxosulphate, Na2S208, etching step.
Dong teaches that the method is free of a sodium peroxosulphate, Na2S208, etching step (Abstract; Paragraphs 0004-0007, 0028, 0033, 0035, 0042, 0058, 0065, 0067).
Dong teaches that it is well known in the art to remove metal oxides by using a wafer processing apparatus that performs an electron attachment process which uses negatively charged atomic hydrogen ions. Neither Lee nor Dong mention using a sodium peroxosulphate, Na2S208, etching step. It would have been obvious to one skilled in the art to perform the method of Lee without a sodium peroxosulphate, Na2S208, etching step, as taught by Dong, in order to easily, efficiently, and economically remove metal oxides.
Regarding Claim 19, Lee does not explicitly disclose the apparatus according to claim 18, being configured as a wafer technology-based apparatus.
Dong teaches the apparatus according to claim 18, being configured as a wafer technology-based apparatus (Abstract; Paragraphs 0004-0007, 0028, 0033, 0035, 0058).
Dong teaches that it is well known in the art to remove metal oxides by using a wafer processing apparatus. It would have been obvious to one skilled in the art to use a wafer technology-based apparatus in Lee, as taught by Dong, in order to easily, efficiently, and economically remove metal oxides.
Relevant Cited Art
The cited art in PTO-892 was found during the examiner's search, but was not relied upon for this office action. However, it is still considered pertinent to the applicant's disclosure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHADAMES J ALONZO MILLER whose telephone number is (571)270-7829. The examiner can normally be reached Mon-Fri 10am-6pm PST.
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/RJA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
