Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 2, 3, 5-7, 19-20, 22, 26, 30, 36-37, 40, 46-48 and 50 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/12/2026.
Applicant's election with traverse of species A in the reply filed on 02/12/2026 is acknowledged. The traversal is on the ground(s) that the species are “related”. This is not found persuasive because while the species may be relevant, they exhibit mutually exclusive characteristics and are non-obvious variants of each other. Furthermore, the different species such as pixel circuits, gate driving circuits, electrode arrangements, etc., have acquired a separate status in the art in view of their different classifications and require a different field of search. As such, the Office maintains that relevancy among the species does not overcome the requirement for elections.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 18 and 52 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al., US 2015/0194110 A1, hereinafter “Park”.
Regarding claim 1, Park teaches a driving circuit (fig. 16, element 70, ¶ 170), comprises: a driving signal generating circuit (fig. 16, element 410, ¶ 171), a control signal generating circuit (fig. 16, element 416, ¶ 171) and a control circuit (fig. 16, element 413, ¶ 171); wherein the driving signal generating circuit is electrically connected to an n-th stage driving signal output terminal (fig. 16, see the Q output of DFF1, for example; ¶ 172), and is used to generate and output an n-th stage driving signal through the n-th stage driving signal output terminal (Q output of each DFF unit is such a driving signal); n is a positive integer; the control signal generating circuit is electrically connected to an enable signal line (fig. 16, ARL, ¶ 174) and a control signal terminal (fig. 16, O1-O4, ¶ 174), and is used to generate a control signal according to an enable signal provided by the enable signal line and output the control signal through the control signal terminal (¶ 174); the control circuit is electrically connected to the control signal terminal, the n-th stage driving signal output terminal and an n-th stage driving output terminal respectively, and is used to output the n-th stage driving signal or invalid voltage signal to the n-th stage driving output terminal under control of the control signal (fig. 16, see AG1 for example which is connected to Q of DFF1, O1 and outputs the driving signal or an invalid signal based on the enable signal, ¶ 171-172 and ¶ 175; also see fig. 17).
Regarding claim 18, Park teaches a display substrate, comprising: a base substrate (lower substrate, ¶ 43) and a driving circuit (fig. 13, element 70) arranged on the base substrate (¶ 135); wherein the display substrate includes a display area (fig. 13, PA) and a peripheral area (fig. 13, areas on substrate 10, other than PA); the driving circuit is arranged in the peripheral area (fig. 13, see element 70); wherein the driving circuit includes the driving circuit of claim 1 (see rejection of claim 1 above).
Regarding claim 52, Park teaches a display device (fig. 13, ¶ 133, LCD device), comprising: the display substrate according to claim 18.
Conclusion
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/SEPEHR AZARI/Primary Examiner, Art Unit 2621