Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendments and Arguments
Amendments and arguments provided on 07/01/2026 have been fully considered and are not found to place the application in a condition for allowance. Specifically, the applicant asserts that “the address signal line ARL of Park cannot be equated with the enable signal line of the present application”. The Office respectfully disagrees. As admitted by the applicant, ARL provides “a basis for the output controller 416 to distribute the scan output enable signal” (see page 2 of remarks, ¶ 3). Indeed, as disclosed by Park, at least in ¶ 173-174, the enable signals are provided in response to the ARL signal line. In other words, ARL functions as an enable signal line.
The applicant has further provided the amendment: “the control circuit comprises a control transistor”. However, such an amendment is non-responsive as it is not supported by the elected species. The specifications provide that “the first control circuit” comprises control transistors, however, the first control circuit is not disclosed in fig. 1 as elected by the applicant. Further, an AND gate utilized in a display device as taught by Park necessarily includes at least one control transistor. Accordingly, the arguments are not found persuasive.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 18 and 52 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al., US 2015/0194110 A1, hereinafter “Park”.
Regarding claim 1, Park teaches a driving circuit (fig. 16, element 70, ¶ 170), comprises: a driving signal generating circuit (fig. 16, element 410, ¶ 171), a control signal generating circuit (fig. 16, element 416, ¶ 171) and a control circuit (fig. 16, element 413, ¶ 171); wherein the driving signal generating circuit is electrically connected to an n-th stage driving signal output terminal (fig. 16, see the Q output of DFF1, for example; ¶ 172), and is used to generate and output an n-th stage driving signal through the n-th stage driving signal output terminal (Q output of each DFF unit is such a driving signal); n is a positive integer; the control signal generating circuit is electrically connected to an enable signal line (fig. 16, ARL, ¶ 174) and a control signal terminal (fig. 16, O1-O4, ¶ 174), and is used to generate a control signal according to an enable signal provided by the enable signal line and output the control signal through the control signal terminal (¶ 174); the control circuit comprises a control transistor (AG1 necessarily includes a transistor) which is electrically connected to the control signal terminal, the n-th stage driving signal output terminal and an n-th stage driving output terminal respectively, and is used to output the n-th stage driving signal or invalid voltage signal to the n-th stage driving output terminal under control of the control signal (fig. 16, see AG1 for example which is connected to Q of DFF1, O1 and outputs the driving signal or an invalid signal based on the enable signal, ¶ 171-172 and ¶ 175; also see fig. 17).
Regarding claim 18, Park teaches a display substrate, comprising: a base substrate (lower substrate, ¶ 43) and a driving circuit (fig. 13, element 70) arranged on the base substrate (¶ 135); wherein the display substrate includes a display area (fig. 13, PA) and a peripheral area (fig. 13, areas on substrate 10, other than PA); the driving circuit is arranged in the peripheral area (fig. 13, see element 70); wherein the driving circuit includes the driving circuit of claim 1 (see rejection of claim 1 above).
Regarding claim 52, Park teaches a display device (fig. 13, ¶ 133, LCD device), comprising: the display substrate according to claim 18.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEPEHR AZARI/ Primary Examiner, Art Unit 2621
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