DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Status of Claims
The amendment filed on 3/16/2026 has been entered. In the amendment, Applicant amended claims 1, 3-4, 8 and 14-15, and added new claim 16. Currently claims 1-16 are pending.
Claim Objections
Claim 1 is objected to because of the following informalities: “according to a General Purpose Input Output (GPIO) command” should be changed to “according to a General Purpose Input Output (GPIO) control command”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2022/0413594) in view of Geng et al. (US 2024/0106977).
Regarding claim 1, Chung teaches a display device (Fig. 10: communication device 3000 including display 3030 reads on a “display device”, which includes application processor AP 3010 that is detailed as IC 10 in Fig. 1) comprising:
a memory (Figs. 1, 4: memory 300);
a processor (Fig. 1 and [0021]: a SoC including host 100 and TMU 230; [0021]: “In some embodiments, the host 100, the CMU 210, the PMU 220, the TMU 230, and the memory 300 may be included in a single chip (e.g., a System-on-Chip (SoC))”; Examiner’s Note: it is optional that the host 100 and the TMU 230 are included in a SoC that reads on a processor) including a temperature sensor (Figs. 1, 4: temperature management unit (TMU) 230; [0028]: “TMU 230 may include a thermistor and/or a temperature sensor”); and
a power supply unit (Fig. 1: PMU 220) for supplying power to the processor (Fig. 1: voltage control signal CTRL_VDD; [0026]: “The PMU 220 may be used to generate a source voltage VDD and adjust an amplitude of the source voltage VDD in response to a voltage control signal CTRL_VDD”; [0057]: “the PMU 220 may provide the source voltage VDD having a magnitude adjusted according to the power control signal CTRL_VDD to the host 100”),
wherein the processor is configured to transmit the ([0030]: “When the temperature of the IC 10 exceeds a reference temperature, the instruction complexity calculation circuit 120 may generate one or more control signal(s) (CTRL) used to adjust an operating voltage level and/or an operating frequency level (hereafter, “voltage-frequency level”) and provide the control signal to the DVFS controller 130; Examiner’s Note: “a temperature value” is read by a temperature value of IC 10 that is compared with a reference temperature), and control a core voltage value (Fig. 1: VDD as “a core voltage value” applied to core 110) of the processor via the power supply unit corresponding to the
Chung does not further teach the control command is in a form of a General Purpose Input Output (GPIO) control command. In the instant invention, the processor includes a GPIO interface configured to control functions of external devices (including the function of controlling a core voltage value of the processor via the power supply unit) by programs.
However, using a GPIO interface in a processor to control functions by programs is not new in the related art.
Geng, for instance, teaches in [0044] a technique of configuring a GPIO interface in a processor to control functions of external devices by programs.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine Geng’s technique with Chung’s technique including a GPIO interface to Chung’s processor and configuring the GPIO interface to control functions, including the function of controlling a core voltage value of the processor via the power supply unit, by programs.
Because there are limited options of interfaces that can be integrated with a processor to control functions of external devcies, one ordinary skill in the art would try any one of the limited options to optimize the performance of a display device.
Regarding claim 2, Chung in view of Ramakrishnan further teach the display device according to claim 1, wherein the memory stores a lookup table (Chung: [0041], “The DVFS controller 130 may also store an amplitude value for the source voltage (e.g., VDD) provided to the core 110 in the memory 300 at defined interval”; [0058], “The memory 300 may include one or more DVFS table(s) 350 listing (e.g.,) voltage-frequency levels, wherein the DVFS governor module 131 may control the CMU driver 132 and the PMU driver 133 with reference to the DVFS table(s) 350”; Fig. 4, DVFS TABLE 350; Figs. 5-6 ) in which a temperature, a core voltage value, and a GPIO control command of the processor are mapped ([0058]-[0062]; Figs. 4-5; Examiner’s Note: complexity C calculated by Equation 1 includes consideration of a temperature on a core voltage value; the result of the calculation results in control signals CTRL, e.g., CTRL1 and CTRL2, that is mapped to corresponding voltages, e.g., V1 and V2, as illustrated in Figs. 5-6).
Regarding claim 3, Chung in view of Ramakrishnan further teach the display device according to claim 2, further comprising a power control circuit module (Chung: Fig. 1, DVFS controller 130) configured to control an output voltage value (Chung: Figs. 1 and 4, VDD) of the power supply unit to be adjusted to the core voltage value corresponding to the transmitted GPIO control command.
Regarding claim 4, Chung in view of Ramakrishnan further teach the display device according to claim 2, wherein the power supply unit includes a power control circuit module (Chung: Figs. 1 and 4, inherent power control circuit module in power supply unit for achieving voltage control in response to voltage control signal CTRL_VDD; [0026], “The PMU 220 may be used to generate a source voltage VDD and adjust an amplitude of the source voltage VDD in response to a voltage control signal CTRL_VDD. For example, the PMU 220 may include a switching regulator generating the source voltage VDD from a voltage provided from an external power source in response to the voltage control signal CTRL_VDD. Here, the PMU 220 may be referred to as a power management integrated circuit (PMIC)”; Examiner’s Note: a switching regulator is an exemplary power control circuit module) configured to control an output voltage value (Chung: Figs. 1 and 4: VDD) to be adjusted to the core voltage value corresponding to the transmitted GPIO control command.
Regarding claim 5, Chung further teaches the display device according to claim 3, wherein the power control circuit module is implemented with a plurality of control circuits (Fig. 4: DVFS governor module 131, CMU driver 132, and PMU driver 133) so that the output voltage value of the power supply unit is applied to the processor as the core voltage value defined in the lookup table.
Regarding claim 6, Chung further teaches the display device according to claim 3, wherein the processor is configured to detect a normal operating voltage value (Figs. 5-6; [0062]: each temperature corresponds to a corresponding complexity, which results in a corresponding operating voltage value) at each temperature defined on the lookup table.
Regarding claim 15, Chung teaches a method of operating a display device (Fig. 10: communication device 3000 including display 3030 reads on a “display device”, which includes application processor AP 3010 that is detailed as IC 10 in Fig. 1) comprising:
generating and storing a lookup table (Fig. 4, DVFS TABLE 350; Figs. 5-6; [0041], “The DVFS controller 130 may also store an amplitude value for the source voltage (e.g., VDD) provided to the core 110 in the memory 300 at defined interval”; [0058], “The memory 300 may include one or more DVFS table(s) 350 listing (e.g.,) voltage-frequency levels, wherein the DVFS governor module 131 may control the CMU driver 132 and the PMU driver 133 with reference to the DVFS table(s) 350”) in which a temperature of a System on Chip (SoC) (Fig. 1: temperature of host 100, part of a SoC; [0021]: “In some embodiments, the host 100, the CMU 210, the PMU 220, the TMU 230, and the memory 300 may be included in a single chip (e.g., a System-on-Chip (SoC))”; Examiner’s Note: TMU 230 of SoC provides a temperature of SoC), a core voltage value (Fig. 6: core voltage value corresponding to a control signal, e.g., CTRL1 and CTRL2 each of which is temperature-related; [0058]-[0062]; Examiner’s Note: complexity C calculated by Equation 1 includes consideration of a temperature on a core voltage value; the result of the calculation results in control signals CTRL, e.g., CTRL1 and CTRL2, that is mapped to corresponding voltages, e.g., V1 and V2, as illustrated in Figs. 5-6) to be applied to the SoC, and a (Figs. 1, 4: voltage control signal CTRL_VDD; Figs. 5-6: exemplary control signal CTRL1 and CTRL2) for applying the core voltage value are mapped;
reading a temperature of the SoC through a temperature sensor (Figs. 1, 4: temperature management unit (TMU) 230) installed in a SoC die ([0021]: “In some embodiments, the host 100, the CMU 210, the PMU 220, the TMU 230, and the memory 300 may be included in a single chip (e.g., a System-on-Chip (SoC))”; Examiner’s Note: TMU 230 of SoC provides a temperature of SoC);
calculating a core voltage value corresponding to the read current temperature of the SoC ([0062]; Figs. 5-6; Examiner’s Note: calculating a core voltage value includes calculating instruction complexity first and determining a corresponding core voltage according to Figs. 5-6 );
generating a (Figs. 1-4: voltage control signal CTRL_VDD) corresponding to the calculated core voltage value and transmitting the(Figs. 1-4: power management unit (PMU) 220); and
controlling a supply power (Figs. 1 and 4: power associated with source voltage VDD) according to the transmitted
Chung does not further teach the control command is a GPIO control command. However, it is not new in the related art using a GPIO control command for controlling the amplitude of an output voltage of a power supply.
Ramakrishnan, for instance, teaches in [0018] it is an option adjusting an output voltage of a power supply via a GPIO control command ([0018]: “some PMICs (Power Management ICs) may offer voltage regulation (such as ADC (Analog-to-Digital Conversion) or GPIO”).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine Ramakrishnan’s technique with Chung’s technique using GPIO control command to control the amplitude of a core voltage value to be applied through the power supply unit.
Because there are limited options aiming at consolidating voltage regulators on the board into an IC, one ordinary skill in the art would try any one of the limited options to optimize the performance of a display device.
Chung does not further teach the control command is in a form of a General Purpose Input Output (GPIO) control command. In the instant invention, the processor includes a GPIO interface configured to control functions of external devices (including the function of controlling a core voltage value of the processor via the power supply unit) by programs.
However, using a GPIO interface in a processor to control functions by programs is not new in the related art.
Geng, for instance, teaches in [0044] a technique of configuring a GPIO interface in a processor to control functions of external devices by programs.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine Geng’s technique with Chung’s technique including a GPIO interface to Chung’s processor and configuring the GPIO interface to control functions, including the function of controlling a core voltage value of the processor via the power supply unit, by programs.
Claims 7-9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2022/0413594) in view of Geng et al. (US 2024/0106977), and further in view of Naito (US 2022/0404895).
Regarding claim 7, Chung in view of Geng does not further teach the display device according to claim 6, wherein the processor is configured to determine a range of a core voltage value to which a first margin is applied to the detected normal operating voltage value.
The differentiating limitation indicates taking into consideration of a necessary tolerance for the production of the processor in terms of its response to a core voltage value applied. The approach is not new, however.
Naito, for instance, teaches in Fig. 5 and [0065]-[0067] determining a range of a core voltage value to which a first margin (Fig. 5: range of core voltage value is defined between normal operating voltage value, e. g., VL1, VL2 or VL3, and sum of normal operating voltage value and voltage margin dVm) is applied to the detected normal operating voltage value.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine Naito’s technique with the technique of Chung in view of Geng to guarantee the operating frequency of the processor at the target frequency (Naito [0067]).
Regarding claim 8, Chung in view of Geng and Naito further teaches the display device according to claim 7, wherein the processor is further configured to detect an occurrence of an event (Chung: [0069] and Fig. 7, start of operation of processor reads on “occurrence of an event”, which is necessarily detected to determine start frequency), and generate a GPIO control command corresponding to a maximum core voltage value (Chung: Fig. 7, start frequency f_s is maximum frequency) according to a type of the detected event and transmit the GPIO control command to the power supply unit (Chung: Fig. 7).
Regarding claim 9, Chung in view of Geng and Naito further teaches the display device according to claim 7, wherein the processor is configured to determine whether the change in temperature measured by the temperature sensor is greater than or equal to a first threshold (Chung: Fig. 7, “first reference temperature (Temp_ref1)”).
Regarding claim 11, Chung in view of Geng and Naito further teaches the display device according to claim 7, wherein the processor is configured to determine whether the change in temperature measured by the temperature sensor is greater than or equal to a first threshold (Chung: Fig. 7, “second reference temperature (Temp_ref2)”).
Regarding claim 12, Chung in view of Geng and Naito further teaches the display device according to claim 11, wherein the processor is configured to call and apply another lookup table (Chung: Fig. 8, step S870) from the memory instead of the previously used lookup table when the change in the temperature is greater than or equal to the second threshold.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2022/0413594) in view of Geng et al. (US 2024/0106977) and Naito (US 2022/0404895), and further in view of Lee (US 2011/0029272).
Regarding claim 10, Chung/Geng/ Naito do not further teach the display device according to claim 9, wherein the processor is configured to adjust a preset temperature measurement cycle to be changed when the change in temperature is greater than or equal to the first threshold.
In the same field of endeavor, Lee teaches in Fig. 2 and [0015]-[0016] adjusting a preset temperature measurement cycle to be changed when the change in temperature is greater than or equal to the first threshold (e.g., “For example, the predetermined range is set to +/-4°C, and the specific temperatures are 48°C, 68°C, and 88°C. Therefore, if the sensed temperature is 50°C., the temperature sensing temperature sensing time interval decreases to 64 µs, and the temperature sensing temperature sensing time interval increases from 64 µs to 128 µs if the sensed temperature is 53°C (the temperature sensing time interval between AB is shorter than the temperature sensing time interval between BC)” in [0016]).
Before the effective filing date of the invention, it would have been obvious to combine Lee’s technique with the technique of Chung in view of Geng and Naito to enable fine tuning for achieving better reliability of thermal measurement.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2022/0413594) in view of Geng et al. (US 2024/0106977) and Naito (US 2022/0404895), and further in view of Choi et al. (WO 2021118009, machine translation of which is used for this examination).
Regarding claim 14, Chung in view of Geng and Naito does not further teach the display device according to claim 7, wherein the processor is configured to transmit log data related to the lookup table to a server, and receive update data of the lookup table according to an analysis of the log data from the server.
The differentiating limitation indicates that the processor is connected to a server and depends on the server for analysis of log data related to the lookup table. The technique is not new in the related art, however.
Choi, for instance, teaches in Fig. 2 that display apparatus 100 configured to transmit log data related to a lookup table to a server, and receive update data of the lookup table according to the analysis of the log data from the server.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine Choi’s technique with the technique of Chung in view of Chung in view of Geng and Naito configuring the processor to transmit log data related to the lookup table to a server, and receive update data of the lookup table according to the analysis of the log data from the server.
The motivation would have to enable the display device to achieve network connectivity that is desirable.
Allowable Subject Matter
Claims 13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629
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