Prosecution Insights
Last updated: October 01, 2026
Application No. 18/997,288

LED DRIVING MODULE

Non-Final OA §103
Filed
Jan 21, 2025
Priority
Jul 22, 2022 — RE 10-2022-0091136 +1 more
Examiner
VU, JIMMY T
Art Unit
2844
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seoul Viosys Co., Ltd.
OA Round
2 (Non-Final)
86%
Grant Probability
Favorable
2-3
OA Rounds
9m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
585 granted / 676 resolved
+18.5% vs TC avg
Moderate +8% lift
Without
With
+7.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
12 currently pending
Career history
689
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
40.4%
+0.4% vs TC avg
§102
37.8%
-2.2% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 676 resolved cases

Office Action

§103
DETAILED ACTION This Office Action is in response to the Applicant’s Amendment filed on 06/24/2026. In virtue of the amendment: Claims 1 and 3-20 are pending in the instant application. Claims 1, 3, 5, 9-11 and 17 are currently amended. The references cited in the Information Disclosure Statement(s) (IDS(s)) filed on 05/22/2026 have been considered by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, filed 06/24/2026, with respect to the rejection(s) of claim(s) 1, 2, 11, 12, 15, 16, 18 and 20 have been fully considered and are partially persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of Jin (U.S. Pub. 2013/0127344 A1) and LOPEZ RODRIGUEZ (hereby LOPEZ) (WO 2023167743 A1). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 11, 12, 15, 16, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin (U.S. Pub. 2013/0127344 A1) in view of LOPEZ RODRIGUEZ (hereby LOPEZ) (WO 2023167743 A1). Regarding claim 1, Jin discloses an LED driving module (Figs. 3 and 9), comprising: a fault sensing unit (fault detection circuit, Fig. 9, par [0066]) configured to sense a fault in an LED (302, Fig. 9), wherein the fault sensing unit comprises a connection sensing unit (elements of circuitry in Fig. 9) configured to sense a connection state (short type faults or open type faults, Fig. 9, pars [0066]-[0068]) of the LED, the connection sensing unit being configured to output a fault signal (922/923, Fig. 9) through a fault signal output terminal (922/923) when a fault occurs due to a short state (Short Detect at 923, Fig. 9) or an open state (Open Detect at 922, Fig. 9) of the LED. Jin does not teach the LED is an ultraviolet LED; and the connection sensing unit includes a connection sensing switch turned on and turned off according to a voltage of a node connected to an anode terminal of the ultraviolet LED. However, as evidenced by LOPEZ, providing the UV LEDs (Fig. 2, each of the LEDs of the plurality may comprise an ultraviolet (UV) LED to output UV light, par [0015]), and the connection sensing unit (fault detection circuit 208, voltage sense circuit 226 and switch 206, Fig. 2, par [0019]) includes a connection sensing switch (switch 206, Fig. 2) turned on and turned off (the fault detection circuit 208 comprises a comparator circuit comprising a first input to connect to the first LED node 210 to receive a first voltage and a second input connected to a terminal of the switch 206 for controlling the conduction of the switch 206, par [0019]) according to a voltage (the first NOR gate 234 comprising a first input 232 to receive the first voltage from first LED node 210, par [0019]) of a node (node 210, Fig. 2) connected to an anode terminal of the ultraviolet LED (node 210 connected to anode of ultraviolet LED 212, Fig. 2) is well known in the art. Therefore, it would have been obvious to one having skill in the art before the filing date of the invention to employ the device of Jin with the UV LED and connection sensing circuit as taught by LOPEZ in order to provide the suitable sensing circuit to control the light emitting of the lighting device with the UV light output. Regarding claim 11, Jin/LOPEZ discloses the LED driving module wherein the connection sensing unit (Fig. 9 of Jin) comprises: an opening sensing unit (e.g., comparator 920, controller turn on switch 914, par [0068] of Jin) configured to sense the open state of the ultraviolet LED; and a short sensing unit (e.g., comparator 921, controller turn on switch 913, par [0067] of Jin) configured to sense the short state of the ultraviolet LED. Regarding claim 12, Jin/LOPEZ discloses the LED driving module wherein each of the opening sensing unit and the short sensing unit comprises: an amplifier (comparators 920 and 921, Fig. 9 of Jin) configured to compare a reference voltage (Open Thrsh 918 and Short Thrsh 919, Fig. 9 of Jin) with an input voltage (voltage through Resd, Fig. 9 of Jin); and at least a switch (913/914, Fig. 9 of Jin) turned on and turned off by an output signal of the amplifier. Regarding claim 15, Jin/LOPEZ discloses the LED driving module wherein the fault signal output terminal outputs a normal signal when the ultraviolet LED is in a normal state (switch 914 is turned off by phase 2 control signal 917 and it remains off during normal operation, par [0068] of Jin). Regarding claim 16, Jin/LOPEZ discloses the LED driving module wherein the fault signal is a lower voltage than the normal signal (If LED string 302 is not properly connected to pin 926, then the voltage at pin 926 will fall to near zero volts, par [0068] of Jin, that meant voltage at pin 926 is lower than Open Thrsh 918, Fig. 9 of Jin). Regarding claim 18, Jin/LOPEZ discloses the LED driving module further comprising: a current sensing unit (Resd, Fig. 9 of Jin) configured to sense a current supplied to the ultraviolet LED (Resd send signal to comparators 920 and 921, Fig. 9 of Jin); and a control signal generator (circuit provides phase control signals, Fig. 9, par [0067]-[0068] of Jin) configured to generate and output a signal to control a switch (913, 914, Fig. 9 of Jin) according to the current sensed by the current sensing unit; wherein the control signal generator outputs a short signal and an open signal to the switch, the short signal turning on the switch, the open signal turning off the switch (par [0067]-[0068] of Jin), the connection sensing unit (Resd, 920, 921, Figs. 9 of Jin) senses the short signal and the open signal output from the control signal generator to the switch (Fig. 9 of Jin), and the fault sensing unit (circuitry in Fig. 9 of Jin) generates and outputs a fault signal (922, 923, Fig. 9 of Jin) when the short signal or the open signal sensed by the connection sensing unit is sensed for a preset period of time or more (during the time the fault signal is detected, pars [0067]-[0068] of Jin). Regarding claim 20, Jin/LOPEZ discloses the LED driving module further comprising: a constant current unit (912, 915, Fig. 9 of Jin) configured to supply a constant current to the ultraviolet LED. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin/LOPEZ, as applied above, in view of HORVATH (DE 102010003506 B4). Regarding claim 17, Jin/LOPEZ discloses all of the limitations as claimed except a Zener diode connected at one end thereof to the fault signal output terminal and at the other end thereof to ground, wherein the normal signal is a Zener voltage. However, as evidenced by HORVATH, providing a Zener diode (D1-DN, Fig. 1, Abstract) connected at one end thereof to the fault signal output terminal (to the evaluation circuit 3, Fig. 1, Abstract) and at the other end thereof to ground (Fig. 1), wherein the normal signal is a Zener voltage (the zener diode breaks and becomes conductive due to the collector current increased in an interruption defect, Abstract, that meant the normal signal is a Zener voltage when there is no interruption) is well known in the art. Therefore, it would have been obvious to one having skill in the art before the filing date of the invention to employ the device of Jin/LOPEZ with the connection of Zener diode as taught by HORVATH in order to provide the signal to the fault detection circuit to inform that there is an interruption defect. Allowable Subject Matter Claims 3-10, 13, 14 and 19 are objected to as being dependent upon the rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Inquiry Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIMMY T VU whose telephone number is (571)272-1832. The examiner can normally be reached on 9:00 AM - 6:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H. Taningco can be reached on 571-272-8048. The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2800. /JIMMY T VU/Primary Examiner, Art Unit 2845
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Prosecution Timeline

Jan 21, 2025
Application Filed
Apr 10, 2026
Non-Final Rejection mailed — §103
Jun 24, 2026
Response Filed
Sep 10, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+7.5%)
2y 5m (~9m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 676 resolved cases by this examiner. Grant probability derived from career allowance rate.

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