Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED OFFICE ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 21, 2025, in compliance with the provisions of 37 CFR 1.97 has been considered by the examiner and made of record in the application file.
Claim Status
Claims 1-20 are pending in this application and are under examination in this Office Action. No claims have been allowed.
Priority
Applicant's claim of priority to Chinese Patent Application No. 202210855906.6, filed July 21, 2022, through International Application No. PCT/CN2023/108358, filed July 20, 2023, under 35 U.S.C. 119(a)-(d), is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claims 5 and 15 expressly recite a delay feedback optical buffer comprising, inter alia, a controller and further recite operation of the first, second, third, and fourth optical amplifiers according to the controller. Figures 2 and 3 illustrate the delay feedback optical buffer structure, including the first and second optical splitters, first and second combiners, first through fourth optical amplifiers, and fiber delay line circulation loop, but do not show the claimed controller. The specification likewise expressly describes the controller as "not shown" in connection with the delay feedback optical buffer. Therefore, the controller recited in claims 5 and 15 is not shown within the drawings. This feature must be shown or the feature canceled from the claim(s). No new matter should be entered.
Figure 1 is further objected to because the drawing repeatedly labels the claimed "label extractor" as "Lable extractor." The drawing terminology should be corrected to "Label extractor" for consistency with the claims and specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the
drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 11 is objected to because of the following informal matter: claim 11 recites "both P and Fare positive integers." The term "Fare" appears to be a typographical error because claim 1 recites the corresponding limitation as "both P and F are positive integers." Appropriate correction is required.
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 3-10 and 13-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 3,
Claim 3 depends from claim 2. Claim 2 recites "optical switching elements respectively corresponding to the various wavelengths" and further recites "the optical switching element corresponding to the wavelength" as the structure configured to store optical packets according to the cache instruction. Claim 3, however, recites "the optical switch corresponding to the wavelength is configured to store" the optical packets in the cache block.
The phrase "the optical switch corresponding to the wavelength" is unclear because the application distinguishes the overall optical switch from the internal optical switching element. The ambiguity is not cured by the specification. Paragraph [0009] describes an "optical switching element corresponding to the wavelength," and paragraph [0084] likewise states that "the optical switching element corresponding to the wavelength" is configured to store the optical packets according to the cache instruction. In contrast, paragraph [0010] uses the different phrase "the optical switch corresponding to the wavelength" for substantially the same storage operation. As written, it is unclear whether claim 3 requires the overall optical switch or the previously-recited optical switching element corresponding to the wavelength to perform the claimed storage operation. Accordingly, the metes and bounds of claim 3 are not reasonably certain, and claim 3 is indefinite.
Regarding claim 13,
Claim 13 contains the same ambiguity. Claim 12 recites "optical switching elements respectively corresponding to the various wavelengths" and further recites "the optical switching element corresponding to the wavelength" as the structure configured to store optical packets according to the cache instruction. Claim 13, however, recites "the optical switch corresponding to the wavelength is configured to store" the optical packets in the cache block.
For the same reasons discussed with respect to claim 3, the intrinsic record distinguishes the overall optical switch from the internal optical switching element corresponding to a wavelength, while the specification itself uses inconsistent terminology for the same storage operation. As written, it is unclear whether claim 13 requires the overall optical switch or the previously-recited optical switching element corresponding to the wavelength to perform the claimed storage operation. Accordingly, the metes and bounds of claim 13 are not reasonably certain, and claim 13 is indefinite.
Regarding claims 4-10 and 14-20,
Claims 4-10 depend directly or indirectly from claim 3 and therefore incorporate the indefinite limitation discussed above.
Claims 14-20 depend directly or indirectly from claim 13 and likewise incorporate the same indefinite limitation. None of these dependent claims resolves whether the claimed storage operation is performed by the overall optical switch or by the optical switching element corresponding to the wavelength.
Accordingly, claims 4-10 and 14-20 are also indefinite under 35 U.S.C. 112(b).
Accordingly, claims 3-10 and 13-20 are indefinite under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 112(d)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS. —Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 12 is rejected under 35 U.S.C. 112(d) as being of improper dependent form because it does not specify a further limitation of the subject matter of the claim from which it depends.
Regarding claim 12,
Claim 12 depends from claim 11. Claim 11 is directed to "A data communication system" comprising at least one data center, at least one terminal, an optoelectronic conversion device, and an optical switch having the recited switching-module, switching-link, cache-group, scheduler, and aggregator structure. Claim 12, however, begins "The optical switch according to claim 11" and is therefore drafted as a claim to the optical switch component rather than as a further limitation of the data communication system claimed in claim 11.
A dependent claim must incorporate all limitations of the claim from which it depends and then further limit that same subject matter. As written, claim 12 changes the subject of the claim from the data communication system of claim 11 to an optical switch and therefore does not properly specify a further limitation of the subject matter claimed in claim 11. To the extent applicant intended to further limit the optical switch that forms part of the data communication system of claim 11, the dependent claim must be drafted so that the data communication system remains the claimed subject matter while the optical switch thereof is further limited.
Accordingly, claim 12 is in improper dependent form under 35 U.S.C. 112(d).
Claim Rejections – 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for the obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains.
Patentability shall not be negated by the manner in which the invention was made.
As reiterated by the Supreme Court in KSR, and as set forth in MPEP 2141 (R-01.2024), II, the factual inquiries of Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), applied for establishing a background for determining obviousness under 35 U.S.C. §103, are summarized as follows:
Determining the scope and content of the prior art;
Ascertaining the differences between the prior art and the claims at issue;
Resolving the level of ordinary skill in the pertinent art; and
Considering objective evidence indicative of obviousness or non-obviousness, if present.
The key to supporting a rejection under 35 U.S.C. § 103 is a clear articulation of the reason or reasons why the claimed invention would have been obvious, with an articulated reasoning having a rational underpinning.
The analysis below identifies the teachings relied upon for each limitation and states a claim-specific reason for the proposed combination.
Prior-art applicability note concerning Yan et al: Yan et al., “Traffic Rate Matrix Decomposition Based Conflict Free Scheduling for a Fast Optical Switching Network,” was published in the OFC 2021 proceedings for the June 6-11, 2021 conference. The present application claims an effective filing date of July 21, 2022. Accordingly, the Yan et al. printed publication predates the claimed effective filing date by more than one year. Although Fulong Yan and Chongjin Xie are also named inventors in the present application, the one-year exception of 35 U.S.C. 102(b)(1) does not remove a disclosure made more than one year before the effective filing date. Yan et al. is therefore relied upon herein as 35 U.S.C. 102(a)(1) prior art.
Claim-construction note for prior-art analysis: Claims 3 and 13 are rejected above under 35 U.S.C. 112(b) because they recite “the optical switch corresponding to the wavelength” where the parent claims and the detailed description identify the relevant internal structure as “the optical switching element corresponding to the wavelength.” For purposes of the prior-art rejections only, and without withdrawing the 35 U.S.C. 112(b) rejection, the disputed phrase in claims 3 and 13, and in claims depending therefrom, is interpreted as referring to the previously recited optical switching element corresponding to the wavelength, consistent with the parent claims and paragraph [0084] of the specification.
Claims 1 and 11 are rejected under 35 U.S.C. § 103 as being unpatentable over Yan et al. (“Traffic Rate Matrix Decomposition Based Conflict Free Scheduling for a Fast Optical Switching Network,” OFC 2021, paper W1E.4) in view of Xu et al. (US 2009/0252493 A1), Lee et al. (US 2005/0063703 A1), Ge et al. (US 6,819,870 B1), and Andriolli et al. (WO 2010/127716 A1), with claim 11 further in view of Bakopoulos et al. (US 2021/0176543 A1).
Claim 1
Yan teaches the claimed scalable optical-switch framework. In Section 2, Yan expressly states: “As shown in Fig. 1(a), the FOS comprising of p modules interconnects N ToRs forming a cluster of p groups. Each group has F = N/p ToRs.” Yan further states that “there are p transceivers (TRXs) in one ToR. Each TRX is responsible for communications with the F ToRs in one group with F logical buffers.” [Yan, p. 2, §2, lines discussing Fig. 1(a)-(c); see also p. 1, Fig. 1(a)-(c)].
Thus, Yan expressly teaches an optical switching fabric divided into p modules, with each module/group servicing F communication links/nodes, and a p-by-F organization whose dimensions are positive integers.
Andriolli makes the wavelength-to-module and module-to-link correspondence explicit. Andriolli teach: “each said routing apparatus comprises a said second plurality of 1xM optical switches. Each said optical switch has one input port and M output ports ... Each of the said optical switches is allocated to a different one of said second plurality of wavelengths. Each of the said optical switches is configurable to route a received optical signal to a selected one of said output ports.” [Andriolli, p. 5; see also claims 4-6, pp. 25-26]. Thus, the wavelength-allocated 1xM optical switches of Andriolli provide the claimed repeated switching-module organization: the number P of such wavelength-specific switching modules corresponds to the number of supported wavelength types, and the M output paths of each module provide the F switching links.
Applying Andriolli’s explicit wavelength-indexed 1xM module arrangement to the p-module fast optical switch of Yan is a direct use of a known wavelength-routing structure for its established purpose.
Yan further teaches the scheduling/control relationship needed for packet-by-packet optical switching.
Yan states that “The FOS controller utilizes von Neumann theorem to transform doubly substochastic traffic rate matrix R into stochastic matrix R0,” that the controller “sends the conflict free transmission slot serials with specific destination” to the transmitting nodes, and that “the optical packets arrive at the FOS, and the FOS is configured with the corresponding matching matrix Pk so that no contention happens.” [Yan, p. 2, §2, steps 1-7].
These teachings establish a controller-driven, slotted optical packet switch in which particular links/paths are selected according to wavelength/channel-group and scheduling information.
Xu supplies the internal wavelength separation, per-egress buffering, combiner, and internal buffer scheduling architecture.
Xu states: “Referring to FIG.3, the network node provided in an embodiment of the present invention includes wavelength division demultiplexer 301, 1xP switch 303, TWC 302, buffer device 304, combiner 305, and control module 306.”
Xu further state: “P egresses of the optical switches 303 are one-to-one corresponding to the P buffer devices 304. One buffer device 304 is corresponding to one egress port, and outputs of the buffer devices 304 are all connected to the combiners 305 at corresponding egress ports. By configuring the optical switches 303, data packets destined for different egress ports are sent to corresponding buffer devices 304 and then sent to the combiners 305 at the egress ports through internal scheduling of the buffer devices 304.” [Xu, ¶ [0051], p. 10; FIG. 3].
Xu also teaches the splitter-to-buffer routing control. The reference states that “A light wave signal bearing data packet control information is transmitted to a control module 306 after a photoelectric conversion. The control module 306 determines an egress port according to a wavelength status table, i.e., determines a corresponding buffer device, and generates a second control signal to control an optical switch 303, so that the light wave signal is transmitted to the corresponding buffer device.” [Xu, ¶ [0051]].
This maps directly to determining a switching destination and storing/routing the optical packet into the cache/buffer group associated with the selected link.
Lee supplies a particularly explicit multi-wavelength splitter, multi-block optical buffer, and wavelength aggregator.
Lee states: “The input device 200 is connected to the N input fibers 100 in order to separate the M-wavelength optical Signal in each fiber into M input optical Signals respective to the M wavelengths.” [Lee, ¶ [0018]].
Lee further states: “The output buffer 500 consists of N delay devices 501 numbered from 0 to (N-1), each having (L+1) optical delay elements 5011 numbered from 0 to L. The (L+1)xN optical delay elements 5011 can be optical fiber delay lines.” [Lee, ¶ [0025]].
These delay devices and their multiple delay elements teach buffer/cache groups containing multiple cache blocks.
Ge makes the claimed wavelength-indexed cache-group organization more explicit.
Ge states: “Each FDL buffer has a set of logic output queues with multi-servers. The number of independent queues is the same as number of output wavelengths.” [Ge, col. 9].
Ge further explains that packets competing for one output are delayed and that the control algorithm schedules packets into the proper FDL-buffer position. [Ge, col. 8, p. 11; FIGS. 2-5].
Accordingly, Ge teaches a separate logical buffering group for each output wavelength, while Xu and Lee teach that each such optical-buffer resource is implemented using multiple basic buffer units / multiple optical delay elements. Combining these teachings yields, for each switching link, F wavelength-associated cache groups, each formed from multiple cache blocks, together with scheduling control for selecting a buffered packet for later output.
Lee also expressly teaches the claimed aggregator function. The reference states: “The optical multiplexer 604 has M input terminals and an output terminal, wherein the M input terminals are connected respectively to the output of each of the converters 603 for merging output optical Signals with wavelengths and accordingly the output terminal outputs a resulting signal with the wavelengths to one of the N output fibers 800.” [Lee, ¶ [0031]].
Thus, Lee teaches combining packet signals of different wavelengths into a single output optical signal.
Ge supplies the explicit “one of the optical packets” scheduling behavior recited by claim 1.
Ge states in the Abstract: “The method includes ordering of each conflicted variable length data packet and Selecting each of the data packets in turn for routing based on the ordering Sequence Selected. The Sequentially assigned conflicted data packet is assigned a wavelength in the FDL optical buffer ... Each data packet is converted to the Sequentially assigned wavelength (n) and routed to an optical buffer according to the wavelength assignment.” [Ge, Abstract,see also p. 9, description of ordering and selecting each packet in turn; FIGS. 2-5].
Ge therefore teaches a scheduler that selects one packet from a set of buffered/conflicted packets and routes that selected packet toward the output.
Accordingly, the cited combination teaches each limitation of claim 1.
Yan provides the scalable p-module/F-link fast optical switching framework and slotted controller-based packet scheduling.
Andriolli provides the express one-wavelength-per-1xM-switch arrangement, with each wavelength-specific optical switch having M output paths, thereby supplying the claimed P wavelength-indexed switching modules and F switching links. Xu provides wavelength demultiplexing, a 1xP routing switch, one-to-one per-egress buffer devices, combiners, a control module, and internal scheduling from the buffer devices to the combiners. Lee provides explicit multi-wavelength separation, multiple optical delay elements within each delay device, and optical multiplexing of the scheduled wavelength signals into a resulting output optical
signal. Ge provides wavelength-indexed logical output queues, FDL-buffer scheduling, and the express step of ordering conflicted packets and selecting packets one at a time for routing. Taken together, the references provide the splitter, the repeated wavelength/link organization,
F cache groups, multiple cache blocks, corresponding scheduling, and the wavelength aggregator recited by claim 1.
One of ordinary skill in the art would have been motivated to combine Yan with Andriolli, Xu, Lee, and Ge because all of the references address the same recognized problem in wavelength-routed optical packet switching: directing simultaneously arriving packets to intended destinations while resolving contention with wavelength routing, buffering, and scheduling. Yan supplies the modular FOS and conflict-free time-slot controller.
Andriolli supplies a known wavelength-indexed bank of 1xM optical switches, each having multiple output links. Xu, Lee, and Ge teach the complementary and well-known technique of retaining a packet that cannot immediately be served in an optical buffer and later selecting it for output. Incorporating the wavelength-indexed switch modules and internal buffering/packet-selection teachings into Yan’s modular FOS would have predictably allowed the switch to preserve contending packets locally while retaining the same wavelength-routing principle of operation. The combination merely places known wavelength-specific 1xM switches, known WDM demultiplexers, known per-wavelength/per-egress queues, known multi-element optical buffers, known schedulers, and known multiplexers into a known modular optical packet switch for their established functions.
This is the predictable use of familiar optical-switching elements according to known methods to obtain the expected result of contention-free or contention-reduced packet delivery.
Claim 11
Claim 11 recites the optical-switch limitations of claim 1 in a data-communication-system environment and further requires at least one data center, at least one terminal, an optoelectronic conversion device communicatively connected to the terminal, and the terminal communicatively connected with an input of the optical switch through the optoelectronic conversion device. The optical-switch limitations are taught by Yan, Andriolli, Xu, Lee, and Ge for the reasons set forth above with respect to claim 1.
Within analogous art, Bakopoulos expressly teaches the additional data-center/terminal/optoelectronic-interface arrangement.
Bakopoulos states: “Introduction of optical switching in the data center has proven to be a nontrivial task due to the idiosyncrasy of optical switches that differ from their electrical counterparts.” [Bakopoulos, ¶ [0046]].
Bakopoulos then states: “The optical network system 10 includes a plurality of optical switches 12, a plurality of host computers 14, optical fibers 16 ... and optionally at least one network controller 18.” [Bakopoulos, ¶ [0055]].
Bakopoulos further states: “The host computers 14 comprise respective optical network interface controllers (NICs) 20 ... The optical fibers 16 connect the optical NICs 20 and the optical switches 12 forming an optically-switched communication network 22.” [Bakopoulos, ¶ [0055], FIG. 1].
Bakopoulos additionally teaches that each optical NIC includes optical transmitter/receiver functionality and a controller that manages packet transmission. [Bakopoulos, ¶¶ [0012], [0016]-[0017], pp. 13-14; FIG. 2].
Thus, the host computer is the claimed terminal, the optical NIC is the claimed optoelectronic conversion/interface device, and the optical fiber connection from the optical NIC to the optical switch is the claimed communication path from the terminal to the optical-switch input through the optoelectronic device.
One of ordinary skill in the art would have been motivated to employ the optical switch rendered obvious for claim 1 in the data-center optical-network environment of Bakopoulos because Bakopoulos expressly identifies data centers as a target environment for optical switching and provides the standard host-computer/optical-NIC/optical-switch interconnection needed to place such a switch into service. The substitution would have involved no change in the basic operation of the switch; the host computer generates packets, the optical NIC performs the electrical/optical and optical/electrical interface functions, and the optical switch routes the resulting optical packets.
Using the known modular buffered switch of the claim-1 combination as the optical switch in Bakopoulos’s known data-center topology would therefore have been a predictable application of a known optical packet switch to its expressly contemplated field of use.
Claim 11 would have been obvious.
Claims 2 and 12 are rejected under 35 U.S.C. § 103 as being unpatentable over the references applied to claims 1 and 11, respectively, and further in view of Liu et al. (CN 102843294 A), with Andriolli et al. additionally relied upon for its label-extractor, wavelength-specific optical-switch, and switch-control teachings.
Claim 2
With respect to claim 2, all limitations of claim 1 are taught by Yan, Andriolli, Xu, Lee, and Ge, except wherein claim 2 additionally expressly teaches that the splitter comprises a separator, a switch controller, wavelength-specific label extractors, and wavelength-specific optical switching elements; that the separator directs each wavelength to its corresponding label extractor; that the label extractor separates/extracts header and payload information; that the header is supplied to the switch controller while the payload proceeds toward the wavelength-specific optical switching element; and that the switch controller determines the switching module from the header and issues the cache/routing instruction. However, within analogous art, Andriolli and Liu teach these additional limitations.
Andriolli expressly teaches the wavelength-specific label-extractor/switch-controller architecture.
Andriolli states: “Each said input module further comprises a label extractor. Said label extractor is arranged to extract said destination labels from transmitted ones of said data cells carried by said optical signals and to generate a further routing control signal for configuring said routing apparatus. The said label extractor is an all-optical label extractor.” [Andriolli, pp. 4-5].
Andriolli further states: “each said routing apparatus comprises a said second plurality of 1xM optical switches ... Each of the said optical switches is allocated to a different one of said second plurality of wavelengths. Each of the said optical switches is configurable to route a received optical signal to a selected one of said output ports.” [Andriolli, p. 5].
Andriolli also expressly teaches the separator and wavelength-specific routing relationship: “The AWG 54 demultiplexes the received multiplexed optical signal and routes each of the individual wavelength components ... to the respective optical switch 32. Each input module 44 further comprises an N channel label extractor 56. And a 90:10 optical splitter ... arranged to route 10% of the multiplexed optical signal to the label extractor 56.” [Andriolli, p. 18].
Andriolli further states that “The switch control unit 28 is further operable to generate a routing control signal ... to provide a destination output module index,” and that the label extractor generates a further routing control signal “for configuring the optical switches 32, to route their respective optical signals to the destination output module 42 identified by the respective destination output module index.” [Andriolli, pp. 18-19].
Liu supplies the explicit optical-header/optical-payload separation and controller processing. Liu state that an OPS core node receives packets for which “the packet header and payload separation of packets” is performed, “extract[s] the packet header information to the control module, for routing addressing and control scheduling,” and the “control module [is] responsible for processing packet header information and issuing the instruction,” while
the OPS switching matrix performs the payload cross-connection according to the instruction. [Liu, ¶ [0012]].
This is the same control-plane/payload-plane division recited by claim 2.
One of ordinary skill in the art would have been motivated to combine Andriolli and Liu with the claim-1 combination because optical packet switches conventionally keep high-rate payload traffic in the optical domain while extracting a relatively small label/header for routing control. Andriolli expressly applies both wavelength-based and label-based routing, and Liu expressly separates the header for electronic/control processing while leaving the payload to be switched optically.
Incorporating that known control-plane separation into the buffered WDM architecture of Yan/Xu/Lee/Ge would have predictably allowed the control module to select the proper module/buffer from the destination information without optoelectronically converting the payload.
The resulting splitter, label-extractor, controller, and wavelength-specific switch arrangement is therefore a straightforward combination of known optical-packet-routing functions. Claim 2 would have been obvious.
Claim 12
For purposes of the prior-art rejection only, and without withdrawing the rejection of claim 12 under 35 U.S.C. 112(d), claim 12 is interpreted as further limiting the optical switch included in the data communication system of claim 11. Under that interpretation, all limitations of
claim 11 are taught by Yan, Andriolli, Xu, Lee, Ge, and Bakopoulos, except wherein claim 12 additionally recites the separator, switch controller, wavelength-specific label extractors,
wavelength-specific optical switching elements, header/payload handling, and controller-issued cache instruction discussed above for claim 2.
Andriolli teaches the same wavelength-specific label extractor, switch control unit, AWG demultiplexer, and 1xM optical switches for the reasons quoted above. [Andriolli, pp. 4-5 and 18-19].
Liu teaches the same separation of packet header and payload, extraction of the header to a control module for routing and scheduling, and control of the optical payload path according to the control instruction. [Liu, ¶ [0012]].
One of ordinary skill in the art would have been motivated to apply these known header-processing and wavelength-specific switching features to the optical switch used in Bakopoulos’s data-center system for the same reasons discussed for claim 2: destination information must be interpreted to select an optical path, while keeping the high-bandwidth payload in the optical domain minimizes conversion overhead.
The data-center context does not alter the known optical-packet-switching function.
Accordingly, claim 12 would have been obvious under the stated interpretation.
Claims 3 and 13 are rejected under 35 U.S.C. § 103 as being unpatentable over the references applied to claims 2 and 12, respectively, and further in view of Wang et al. (CN 103685078 A).
Claim 3
With respect to claim 3, all limitations of claim 2 are taught by Yan, Xu, Lee, Ge, Andriolli, and Liu, except wherein claim 3 additionally expressly teaches that a wavelength-associated cache group contains multiple cache blocks, that different cache blocks correspond to different switching links, and that the cache instruction identifies the cache block corresponding to the selected switching link. However, within analogous art, Andriolli, Xu, and Wang teach the additional per-output/per-flow buffer partitioning and selection.
Andriolli expressly teaches an input-buffer organization having separate logical queues for different output destinations: “Each said optical transmitter is provided with an input buffer, comprising said first plurality multiplied by said second plurality of virtual output queues. The synchronous packet switch therefore stores data cells received in the electrical domain in virtual output queues ... The module control unit thereby performs intra-module scheduling of data cells for transmission.” [Andriolli, p. 6].
Thus, Andriolli teaches multiple distinct buffer blocks/queues whose identity is tied to a particular output destination/link and whose contents are selected by a scheduler/control unit.
Xu teaches that a buffer device itself contains multiple basic buffer units and that the scheduler selects/reserves the particular basic buffer units making up the selected path.
Xu states: “A scheduling method for transmitting a data packet in an optical network is provided,” including determining a path and “judg[ing] whether each of basic buffer units is capable of being reserved according to egress port status information.” [Xu, ¶¶ [0022]-[0024]].
The reference further teaches that a data packet is transmitted through the selected path after the required basic buffer units have been reserved. [Xu, ¶¶ [0024]-[0029]].
Wang makes the per-flow grouping still more explicit.
Wang states: “The M delay lines are divided into N groups, each group of light fibre delay belongs to one flow controller according to the following rule scheduling light packet,” and then schedules the remaining packets into the first through M-th optical-fiber delays according to priority. [Wang, ¶¶ [0015]-[0025]].
Wang therefore teaches partitioning multiple buffer elements according to the logical flow/output path that they serve.
One of ordinary skill in the art would have been motivated to map individual buffer blocks to individual switching links in the claim-2 architecture because that is the ordinary way to prevent head-of-line interference among packets destined for different outputs. Andriolli uses virtual-output queues for exactly that purpose, Xu chooses particular basic buffer units along a scheduled path, and Wang groups FDL resources by flow. Implementing each cache block as the block assigned to the corresponding switching link would therefore have been a predictable bookkeeping and physical-routing arrangement that permits the controller to issue a cache instruction identifying the exact link-specific block to be used. Claim 3 would have been obvious.
Claim 13
With respect to claim 13, all limitations of claim 12, as interpreted for prior-art purposes, are taught by Yan, Andriolli, Xu, Lee, Ge, Bakopoulos, and Liu, except wherein claim 13 additionally recites the multiple-cache-block/link correspondence and cache-instruction selection discussed above for claim 3.
However, within analogous art, Andriolli teaches multiple virtual output queues mapped to destinations [Andriolli, p. 6].
Xu teaches multiple reservable basic buffer units along a selected path [Xu, ¶¶ [0022]-[0029]].
Additionally, Wang teaches delay-line resources divided into groups associated with respective flows. [Wang, pp. 3-5].
One of ordinary skill in the art would have been motivated to apply the same per-link buffer-block mapping in the claim-11 data-center optical switch because packets destined for different links still require independent queueing/buffering resources regardless of the surrounding system.
The use of link-indexed cache blocks would predictably preserve packet ordering and isolate contention among links.
Claim 13 would therefore have been obvious.
Claims 4 and 14 are rejected under 35 U.S.C. § 103 as being unpatentable over the references applied to claims 3 and 13, respectively, and further in view of Callegati et al. (“Scheduling Algorithms for a Slotted Packet Switch with either Fixed or Variable Length Packets,” Photonic Network Communications 8(2), 2004).
Claim 4
With respect to claim 4, all limitations of claim 3 are taught by Yan, Xu, Lee, Ge, Andriolli, Liu and Wang, except wherein claim 4 additionally expressly teaches that the cache block comprises a delay feedback optical buffer. However, within analogous art, Callegati expressly teaches this exact optical-buffer type.
Callegati states in the Abstract: “We consider a fairly generic all-optical packet switch architecture with a feedback optical buffer constituted of fibre delay lines.” [Callegati, Abstract, p. 1].
In describing the router architecture, Callegati further states: “To help solving contention ... an optical buffer is implemented using Fibre Delay Lines (FDLs). To allow sharing of these resources, a feedback buffer configuration was chosen: B·k ports of the switch fabric are used to lead packets to the FDLs ... After having been delayed in the FDLs, packets will re-enter the switch fabric to have another try at being forwarded to the correct output fibre.” [Callegati, §2, p. 4, Fig. 1].
Xu independently confirms the same feedback/closed-loop architecture. Xu teaches that “the internal switching unit and the basic buffer unit form a closed connection by alternating with each other,” and that the basic buffer unit buffers the light wave from the internal switching unit. [Xu, ¶¶ [0009]-[0016]].
These disclosures are the conventional feedback-buffer operation recited by claim 4.
One of ordinary skill in the art would have been motivated to implement the cache block of claim 3 as the feedback FDL buffer taught by Callegati and Xu because both references expressly identify feedback FDLs as a solution for optical-packet contention where random-access optical memory is unavailable.
A feedback FDL allows a contending packet to circulate and retry the output later without converting the payload to electronic memory. Applying that known buffer type to the link-specific cache block of the claim-3 combination would have predictably provided the desired optical delay and later re-scheduling function.
Claim 4 would have been obvious.
Claim 14
With respect to claim 14, all limitations of claim 13 are taught by Yan, Xu, Lee, Ge, Andriolli, Bakopoulos, Liu, and Wang, except wherein claim 14 additionally recites that the cache block comprises a delay feedback optical buffer.
However, within analogous art, Callegati expressly teaches “a feedback optical buffer constituted of fibre delay lines,” with packets recirculated through FDLs and returned to the switch for another forwarding attempt. [Callegati, Abstract, p. 1; §2, p. 4, Fig. 1].
Xu independently teaches the closed-loop internal-switch/basic-buffer connection. [Xu, ¶¶ [0009]-[0016]].
One of ordinary skill in the art would have been motivated to use this known feedback FDL buffer in the data-center switch for the same contention-resolution reasons discussed for claim 4. Claim 14 would therefore have been obvious.
Claims 5 and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over the references applied to claims 4 and 14, respectively, and further in view of Park et al. (“An Integrated Recirculating Optical Buffer,” Optics Express 16(15), 2008) and Burmeister et al. (“SOA Gate Array Recirculating Buffer with Fiber Delay Loop,” Optics Express 16(12), 2008).
Claim 5
With respect to claim 5, all limitations of claim 4 are taught by Yan, Xu, Lee, Ge, Andriolli, Liu, Wang, and Callegati, except wherein claim 5 additionally expressly teaches the specific two-splitter/two-combiner/four-amplifier recirculating-buffer topology and selective amplifier control. However, within analogous art, Park and Burmeister teach the additional optical-buffer topology.
Park expressly teaches the recirculating delay line and the four-amplifier two-splitter gate matrix. Park states: “Figure 1(a) shows a layout of the integrated device. This is a recirculating optical buffer structure consisting of a silicon delay line and a gate matrix switch with additional boost amplifiers. Once optical packets are routed into the delay line, they are stored in the delay line until the gate matrix switch re-routes them to the output.” [Park, p. 2, Fig. 1(a)].
Park then states: “The 2x2 gate matrix switch consists of two MMI splitters and four switching amplifiers. Input packets are split into two output ports and one of the split signals is gated by the amplifiers to a desired output port as illustrated in Fig. 1(b). Since this is based on a broadcast-and-selection method, there is an inherent loss of 6 dB from the input splitters and the output combiners.” [Park, p. 2, Fig. 1(b)]. This expressly provides two splitters, four switching amplifiers, and two output-combiner paths in the same 2x2 buffer switch.
Park’s FIG. 1(b) also maps the claimed interconnections element-by-element. The upper “Loop out” port enters a first 1x2 MMI splitter; the two branches of that splitter feed two of the four gate/switching amplifiers. Those amplifier paths terminate at the two right-side combining junctions, one of which feeds “Loop in” and the other of which feeds “Output.” The lower external “Input” port enters the second 1x2 MMI splitter; its two branches feed the remaining two switching amplifiers, which likewise terminate at the same two combining junctions. [Park, p. 2, FIG. 1(a)-(b)].
Numbering the loop-side splitter as the claimed first splitter, the external-input splitter as the claimed second splitter, the loop-side combining junction as the claimed first combiner, and the external-output combining junction as the claimed second combiner gives the recited connections: loop output -> first splitter; first-splitter branches -> first/second amplifiers; first amplifier -> first combiner and second amplifier -> second combiner; first combiner -> delay-line loop; external optical packet input -> second splitter; second-splitter branches -> third/fourth amplifiers; third amplifier -> first combiner and fourth amplifier -> second combiner; and second combiner -> external output path. Thus, the physical topology of Park is not merely similar in function; FIG. 1(b) provides the same two-input/two-output splitter/amplifier/combiner cross-coupling recited by claim 5.
Burmeister independently teaches the fiber-delay circulation loop and on/off amplifier gating. Burmeister states: “The buffer approach combines a two-by-two InP-based switch with 450 centimeters of fiber (Fig. 1).” [Burmeister, p. 2].
Burmeister further states: “During operation, the signal is split toward the two possible output ports, and the switching amplifier is turned on for the desired path while the other path’s amplifier is left off to absorb the remainder.” [Burmeister, p. 3, Fig. 1].
Burmeister later confirms that “The InP-based switch demonstrated successful optical buffering of packets when combined with a fiber recirculation loop.” [Burmeister, p. 5].
The connection arrangement shown in Park, Fig. 1(a)-(b), and Burmeister, Fig. 1, teaches the same functional topology recited by claim 5: one gate path directs the packet into the delay loop/recirculation path and another gate path directs the packet to the output; the loop returns the delayed packet to the switching gate for a later circulation decision. The parent combination already provides the scheduler/control module that decides whether the buffered packet should continue to be delayed or should be sent to the output. For purposes of the prior-art rejection, the claim phrase “the output end of the second combiner is connected to an output end of the scheduler” is interpreted consistently with the specification’s operational description as requiring the second-combiner output to be coupled on the scheduler/output path, because the specification states that the packet is output “to a scheduler through the second combiner.”
One of ordinary skill in the art would have been motivated to use Park’s two-splitter/four-amplifier/two-combiner gate matrix and Burmeister’s fiber-delay loop as the physical implementation of the feedback buffer already taught by Callegati and Xu, Park expressly identifies the design as an integrated recirculating optical buffer and Burmeister expressly demonstrates the same class of SOA gate-array buffer with a fiber delay loop. Replacing a generic 2x2 optical switch in a known feedback FDL buffer with the known SOA gate matrix of Park/Burmeister would have predictably provided fast nanosecond switching, optical gain to offset loop loss, and simple binary selection between recirculation and output. The parent controller/scheduler would naturally provide the gate-control signals that turn the appropriate amplifiers on and off. This is a direct and predictable implementation choice within the same optical-buffer art.
Claim 5 would have been obvious.
Claim 15
With respect to claim 15, all limitations of claim 14 are taught by Yan, Xu, Lee, Ge, Andriolli, Bakopoulos, Liu, Wang and Callegati, except wherein claim 15 additionally recites the same two splitters, two combiners, four optical amplifiers, controller, and fiber-delay circulation loop recited by claim 5.
However, Park expressly teaches a recirculating optical buffer having “two MMI splitters and four switching amplifiers” and “output combiners,” [Park, p. 2, Fig. 1].
while Burmeister teaches the same 2x2 SOA gate-array concept used with a “fiber delay loop” and selective on/off gating of the amplifiers. [Burmeister, pp. 2-3, Fig. 1].
For the same reasons discussed with respect to claim 5, one of ordinary skill in the art would have been motivated to employ the Park/Burmeister SOA gate-matrix recirculating buffer in the claim-14 data-center optical-switch architecture. Claim 15 would therefore have been obvious.
Claims 6, 8, 16, and 18 are rejected under 35 U.S.C. § 103 as being unpatentable over the references applied to claims 4 and 14, respectively, and further in view of Callegati et al. and Burmeister et al. for optical-buffer dimensioning and packet-length/rate considerations.
Claim 6
With respect to claim 6, all limitations of claim 4 are taught by Yan, Xu, Lee, Ge, Andriolli, Liu, Wang, and Callegati, except wherein claim 6 additionally expressly teaches determining cache-block storage space according to Ld, L, and r, where Ld is the maximum number of bits simultaneously carried on the input link, L is the number of bits in an optical packet, and r is the packet-switching/service rate. However, within analogous art, Callegati and Burmeister teach that optical-buffer capacity is dimensioned according to these same result-effective traffic, packet-length, and service-rate parameters.
Callegati expressly identifies the physical buffer-dimension parameters.
In Table I, Callegati identifies “B number of FDLs,” “k number of wavelengths per FDL,” “R number of re-circulations allowed in the FDL buffer,” and “D granularity of the delay lines.” [Callegati, p. 4, Table I].
Callegati further states: “the value of P indicates how many packets may be entered into the buffer each timeslot,” where P=B·k, and explains that the number of recirculation ports and available delays determine how much packet traffic can be accepted by the buffer in a slot. [Callegati, p. 5].
Callegati also expressly ties buffer delay to packet length: “A study of the optimal choice of delay granularity compared to packet length ... [concludes] that there is an optimal choice for the delay granularity: when it is too small (compared to the average packet length), the chance a packet can be delayed long enough ... is small. On the other hand, when D is large compared to the packet length, packets will be delayed longer than necessary.” [Callegati, p. 5].
Thus, packet length L is a known buffer-sizing variable.
Burmeister likewise expressly ties buffer capacity to packet length and data/switching rate. Burmeister states: “It is necessary that a buffering approach can impart a delay of at
least the length of the packet payload in order to provide contention resolution,” and the buffer must be “bit rate scalable to 40 Gb/s or greater.” [Burmeister, p. 2].
Burmeister further states: “Simulations show that if access links are slower than the backbone network and the traffic is smoothed, then only ten packet buffers per output port are needed for 80% throughput.” [Burmeister, p. 2].
This directly teaches sizing the buffer from packet size, aggregate arrival/link capability, and service/throughput rate.
In the claim-1 combination, Yan teaches p parallel transceivers/wavelength paths and slotted service, so the maximum number of bits that can arrive simultaneously on a link is a direct function of the number of simultaneously active wavelength channels and packet length.
The cited art therefore treats the same physical quantities represented by Ld, L, and r as the variables that determine how much optical buffering is necessary.
One of ordinary skill in the art would have been motivated to calculate or select the storage capacity from those parameters because excessive optical buffering increases loss, cost, footprint, and ASE accumulation, while insufficient buffering increases packet loss. Selecting the minimum capacity that supports the expected simultaneous arrivals at the known packet size and switching rate is a routine optimization of known result-effective variables.
Claim 6 would have been obvious.
Claim 8
With respect to claim 8, all limitations of claim 4 are taught by Yan, Xu, Lee, Ge, Andriolli, Liu, Wang, and Callegati, except wherein claim 8 additionally expressly teaches that the amount of delay-feedback optical buffers is determined according to Ld and L. However, within analogous art, Callegati expressly defines B as the “number of FDLs,” k as the “number of wavelengths per FDL,” and P=B·k as the number of packets that may enter the buffer each timeslot. [Callegati, pp. 4-5, Table I].
Burmeister expressly discusses the number of packet buffers required per output port and states that “only ten packet buffers per output port are needed for 80% throughput” under the stated link-capacity conditions. [Burmeister, p. 2].
Thus, the cited art expressly teaches choosing the number of optical buffer elements based on the amount of packet traffic that can arrive and the packet payload that each buffer must hold. In the combined WDM switch, Ld/L is simply the maximum simultaneous packet-equivalent load on the link.
It would have been obvious to use that packet-equivalent load to determine how many one-packet or packet-sized delay buffers are required.
Claim 8 would have been obvious.
Claim 16
With respect to claim 16, all limitations of claim 14 are taught by Yan, Xu, Lee, Ge, Andriolli, Bakopoulos, Liu, Wang and Callegati, except wherein claim 16 additionally recites the same Ld/L/r-based storage-space determination as claim 6.
However, Callegati teaches selecting FDL number, wavelength capacity, recirculation, and delay granularity according to packet-arrival capacity and packet length [Callegati, pp. 4-5].
Additionally, Burmeister teaches that optical-buffer delay must be at least a packet payload and that the number of packet buffers required depends on access/core link rate and desired throughput. [Burmeister, p. 2].
For the same result-effective-variable and routine-dimensioning reasons discussed with respect to claim 6, one of ordinary skill in the art would have determined the cache-block storage in the claim-14 system from the maximum simultaneous packet load Ld, the packet size L, and the switch service rate r. Claim 16 would therefore have been obvious.
Claim 18
With respect to claim 18, all limitations of claim 14 are taught by Yan, Xu, Lee, Ge, Andriolli, Bakopoulos, Liu, Wang and Callegati, except wherein claim 18 additionally recites that the amount of delay-feedback optical buffers is determined according to Ld and L. However, Callegati teaches that the number B of FDLs and the number k of wavelength positions per FDL establish how many packets may be admitted to the buffer in a time slot [Callegati, pp. 4-5].
While Burmeister expressly identifies a required number of packet buffers per output under specified link-rate/load conditions [Burmeister, p. 2].
One of ordinary skill in the art would have been motivated to choose the number of delay-feedback buffers as a function of the maximum number of packet-equivalents that may simultaneously appear on the input link, Ld/L, because each packet-sized delay-buffer resource can hold a finite packet payload and the required number of resources increases with simultaneous packet demand.
Claim 18 would therefore have been obvious.
Claims 7, 9, 17, and 19 are rejected under 35 U.S.C. § 103 as being unpatentable over the references applied to claims 6, 8, 16, and 18, respectively, further in view of the numerical buffer-depth teachings of Burmeister et al. and the expressly variable M-wavelength single-fiber architecture of Lee et al., with Yan et al.’s p=4 operating example further corroborating the routine multi-channel operating point.
Claim 7
For purposes of the prior-art rejection only, and without withdrawing the rejection of claim 7 under 35 U.S.C. § 112(b).
With respect to claim 7, all limitations of claim 6 are taught by Yan, Xu, Lee, Ge, Andriolli, Liu, Wang, and Callegati, except wherein claim 7 additionally expressly limits the cache-block storage space to no more than (4+2*Ld/L-r)*L. However, within analogous art, Burmeister teaches a concrete small-buffer operating point that falls within the claimed upper-bound relationship when applied to the multi-wavelength slotted architecture of Yan.
Lee expressly discloses a single physical input fiber carrying a selectable number M of wavelength channels.
Lee states: “Each of the N input fibers can transmit an M-wavelength optical signal which has M wavelengths ... where M, N are positive integers.” [Lee, ¶ [0009]].
Lee therefore expressly teaches a design family in which the number of simultaneous wavelength channels M is a positive design integer; selecting M=4 is an ordinary species directly within that disclosed architecture.
Yan independently corroborates a four-way optical implementation by expressly using “a cluster of 320 servers (N = 8, p = 4)” and p parallel transceivers/channels. [Yan, pp. 2-3].
In the four-wavelength, fixed-packet-length species of the combined WDM switch, four equal-L packets can be carried simultaneously on the input fiber, giving a maximum simultaneous packet-equivalent input of Ld/L=4.
Burmeister teaches that “only ten packet buffers per output port are needed for 80% throughput” when the access links are slower than the backbone and traffic is smoothed. [Burmeister, p. 2].
Burmeister also teaches that each buffer must provide at least the delay of the packet payload and describes packet buffers in packet-size terms. [Burmeister, p. 2].
Thus, ten packet buffers correspond to approximately 10L of packet storage for fixed-L packets.
For purposes of the prior-art rejection, r is interpreted consistently with the claim/specification as the packet service/switching rate expressed per switching interval. The slotted optical switch of Yan schedules one packet on the relevant wavelength/link in a switching slot; thus, for the relevant cache group, the normalized service rate is r=1 packet per switching interval. With the expressly permitted four-wavelength single-fiber species of Lee, Ld/L=4.
The claimed upper bound is therefore (4+2(4)-1)L=11L. Burmeister ’s expressly taught ten-packet buffer bank corresponds to approximately 10L of packet storage for fixed-L packets, which satisfies 10L≤11L. The cited art therefore provides a concrete prior-art operating point lying within the claimed upper-bound limitation, while the parent references provide the recited optical-switch/cache architecture.
Moreover, even apart from that overlapping numerical species, the cited art teaches the general condition and the optimization objective: use as few optical packet buffers as possible while maintaining the desired throughput and contention-loss performance. Burmeister expressly emphasizes reducing buffer count because the number of optical buffers affects “cost, footprint, and energy consumption,” [Burmeister, p. 2].
While Callegati teaches optimizing FDL length and number against packet length and accepted packet loss [Callegati, pp. 4-5].
Once Ld, L, and r were recognized result-effective variables, selecting an upper-bound storage capacity within the known workable range would have been routine optimization. Claim 7 would have been obvious.
Claim 9
For purposes of the prior-art rejection only, and without withdrawing the rejection of claim 9 under 35 U.S.C. § 112(b).
With respect to claim 9, all limitations of claim 8 are taught by Yan, Xu, Lee, Ge, Andriolli, Liu, Wang, and Callegati, except wherein claim 9 additionally expressly limits the amount of delay-feedback optical buffers to no more than 4+2*Ld/L. However, the same prior-art operating point falls directly within this claimed upper bound.
As discussed above, Lee expressly permits an M-wavelength signal on a single input fiber, with M a positive integer, and selection of M=4 gives Ld/L=4 for four simultaneously carried equal-L wavelength packets. Yan ’s independent p=4 example further confirms that four parallel optical channels was an ordinary operating point. The claimed numerical upper bound therefore becomes 4+2(4)=12 delay-feedback buffers.
Burmeister expressly teaches that “only ten packet buffers per output port are needed for 80% throughput.” [Burmeister, p. 2].
Ten is less than or equal to twelve.
Accordingly, a ten-buffer prior-art implementation falls within the numerical scope of claim 9.
One of ordinary skill in the art would have been motivated to use ten rather than twelve buffers because Burmeister expressly identifies reduced buffer count as desirable for cost, footprint, power, and signal-quality reasons, while still achieving substantial throughput. Selecting the smaller known sufficient count would have been a routine design choice yielding the predictable result of reduced hardware with acceptable throughput. Claim 9 would therefore have been obvious.
Claim 17
For purposes of the prior-art rejection only, and without withdrawing the rejection of claim 17 under 35 U.S.C. § 112(b).
With respect to claim 17, all limitations of claim 16 are taught by Yan, Xu, Lee, Ge, Andriolli, Bakopoulos, Liu, Wang and Callegati, except wherein claim 17 recites the same storage-space upper bound (4+2*Ld/L-r)*L as claim 7. The same numerical and optimization analysis therefore applies.
However, within analogous art, Lee supplies the expressly variable M-wavelength single-fiber architecture; choosing the ordinary four-wavelength species gives Ld/L=4 for fixed-L packets [Lee, ¶ [0009]].
Yan independently corroborates four-way optical operation [Yan, pp. 2-3].
Burmeister supplies a ten-packet buffer depth, and the slotted one-packet-per-wavelength service operation gives r=1 per switching interval. The resulting claimed upper bound is 11L, within which the 10L prior-art buffer bank falls [Burmeister, p. 2].
For the same reasons set forth in detail for claim 7, one of ordinary skill in the art would have been motivated to select that known small-buffer operating point in the claim-16 system. Claim 17 would therefore have been obvious.
Claim 19
For purposes of the prior-art rejection only, and without withdrawing the rejection of claim 19 under 35 U.S.C. § 112(b).
With respect to claim 19, all limitations of claim 18 are taught by Yan, Xu, Lee, Ge, Andriolli, Bakopoulos, Liu, Wang and Callegati, except wherein claim 19 recites the same numerical maximum amount of delay-feedback optical buffers, 4+2*Ld/L, as claim 9.
In Lee’s expressly disclosed M-wavelength single-fiber architecture, selecting the ordinary M=4 species yields Ld/L=4 for four simultaneously carried equal-L wavelength packets, and the claimed maximum is therefore twelve buffers. [Lee, ¶ [0009]].
Yan’s p=4 optical-channel example corroborates that four-way operation [Yan, pp. 2-3].
Burmeister expressly teaches ten packet buffers per output [Burmeister, p. 2].
Because ten is within the claimed maximum of twelve and because the art expressly motivates minimizing the number of optical buffers while maintaining throughput, the subject matter of claim 19 would have been obvious for the same reasons stated with respect to claim 9.
Claims 10 and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over the references applied to claims 4 and 14, respectively, and further in view of Zhao (CN 101672952 A) and Liu et al.
Claim 10
With respect to claim 10, all limitations of claim 4 are taught by Yan, Xu, Lee, Ge, Andriolli, Liu, Wang, and Callegati, except wherein claim 10 additionally expressly teaches that, when there are two or more delay-feedback optical buffers, the two or more delay-feedback optical buffers are connected in series. However, within analogous art, Zhao and Liu expressly teach series/cascaded multi-stage recirculating FDL buffers.
Zhao states in the Abstract that the disclosed “multistage ringed optical fibre delay line cache structure” is “composed of multiple single stage ringed optical fibre delay line cache structure in series.” [Zhao, Abstract, p. 1].
Zhao further states that, in the multistage structure, “each level cache structure are connected into a ring” and that the stages provide progressively different cache granularity. [Zhao, pp. 3-4]. Claim 1 of Zhao likewise recites “multiple single stage ringed optical fibre delay line cache structure in series.” [Zhao, claim 1, pp. 4-5].
Liu independently teaches cascaded feedback-buffer groups. Liu states that an FDL ring buffer device is “orderly connected to form an annular by multiple FDL buffer group,” and that “upper basic input port of the basic output port of an FDL buffer group [is] cascaded [to the] lower one FDL buffer group.” [Liu, ¶ [0005]].
Liu further teaches that adjacent FDL buffer groups may be cascaded to obtain a longer buffer time. [Liu, ¶¶ [0024]-[0030]].
One of ordinary skill in the art would have been motivated to connect two or more feedback buffers in series because Zhao and Liu expressly identify cascading as the known way to obtain longer and more finely selectable optical delays without requiring one extremely long delay element. Cascading preserves the same recirculating FDL principle while extending the achievable buffer depth and allowing staged capacity expansion. Applying that known series connection to the delay-feedback buffers of claim 4 would have predictably increased available buffering time/capacity. Claim 10 would have been obvious.
Claim 20
With respect to claim 20, all limitations of claim 14 are taught by Yan, Xu, Lee, Ge, Andriolli, Bakopoulos, Liu, Wang and Callegati, except wherein claim 20 additionally recites the same series connection of two or more delay-feedback optical buffers recited by claim 10.
However, Zhao expressly teaches multiple single-stage ring FDL buffer structures “in series,” [Zhao, Abstract and claim 1].
Additionally, Liu teaches multiple FDL buffer groups cascaded in sequence and capable of providing longer combined delay [Liu, pp. 2-7].
For the same reasons discussed in detail with respect to claim 10, one of ordinary skill in the art would have been motivated to employ a series/cascaded arrangement in the claim-14 data-center optical switch to increase delay range and buffering capacity while retaining modular control. Claim 20 would therefore have been obvious.
Accordingly, claims 1-20 are rejected under 35 U.S.C. § 103 on the grounds set forth above.
It is noted that any citations to specific pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Conclusion
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/MOHAMMED ABDELRAHEEM/
Examiner, Art Unit 2635
/DAVID C PAYNE/Supervisory Patent Examiner, Art Unit 2635
