DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-9, 11-13, 15 & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rizzo (US 2011/0058397) in view of Hodge, Jr. (US 2002/0080630).
With regard to claim 1, Rizzo, in Figure 1, discloses a current limiter circuit (Abstract) for controlling current between a power supply source (104) and a power supply capacitor (122) of a power supply (102), the circuit comprising an input node connectable to the power supply source (104); an output node connectable to the power supply capacitor (122); a first MOSFET transistor (112, paragraph 0027) and a second MOSFET transistor (118, paragraph 0025) coupled in series between the input node and the output node; a current limiter element (106) coupled in parallel with the second MOSFET transistor (118); a controller (116) comprising a controller output for controlling operations of the first (112) and second (116) MOSFET transistors; and a delay circuit (as shown in 716 of Fig. 7, a delay circuit not shown in Fig. 1 allows a current limiting time delay to elapse), said delay circuit for providing a time delay to signals at the controller output (paragraph 0031); wherein during powering up of the power supply source, the controller is configured to switch on the first MOSFET transistor (112) such that current flows between the input node and the output node via the current limiter element (paragraphs 0047-0049); and switch on the second MOSFET transistor after the time delay, such that current flows between the input node and the output node bypassing the current limiter element (paragraphs 0049 & 0050).
Rizzo does not specifically teach that the delay circuit is coupled to the controller output.
Hodge, Jr., in Figure 3, teaches an inrush current limiting circuit similar to Rizzo wherein a resistor (83) is provided to power to a load during startup and a controller sends a signal to bypass the resistor with a MOSFET (82) when it is determined that power is present at an input. The signal is delayed, allowing for the inrush current to resolve. It is further taught that the delay can be a dedicated delay circuit coupled with the output of the controller (paragraph 0022).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Rizzo with Hodge, Jr, by providing the delay of Rizzo as a delay circuit coupled to the output of the controller as taught by Hodge, Jr, for the purpose of providing a simple means to provide a delay that does not use processing power.
With regard to claims 2-5, 7 & 8, Rizzo in view of Hode, Jr discloses the device of claim 1, and further discloses that the input terminal of the first MOSFET transistor is coupled to the input node; an output terminal of the first MOSFET transistor is coupled to the input terminal of the second MOSFET transistor; and an output terminal of the second MOSFET transistor is coupled to the output node (as seen in Fig. 1 of Rizzo) (re claim 3), wherein the current limiter element comprises a resistor connected in parallel with the input and output terminals of the second MOSFET transistor (Rizzo, paragraph 0033) (re claim 4), wherein the controller comprises a controller input coupled to the output node (through 108, 110, 112 & 126); and wherein the controller output is coupled to respective gate terminals of the first and second MOSFET transistors (as seen in Fig. 1 of Rizzo) (re claim 5), wherein the time delay is a time period for the power supply capacitor to be sufficiently charged when current flows through the current limiter element (Rizzo, paragraph 0050) (re claim 7), wherein the first and second MOSFET transistors are PMOS transistors (while the reference does not specifically mention that the MOSFET transistors are PMOSFET transistors, the transistors would be either PMOSFET on NMOSFET devices and it would have been obvious to one of ordinary skill in the art at the time that the invention was filed to try either polarity of MOSFET as both choices are known equivalents of each other with similar results) (re claim 8).
With regard to claim 9, Rizzo teaches a method of controlling current between a power supply source (104) at an input node of a current limiter circuit (Abstract) and a power supply capacitor (122) of a power supply at an output node of the current limiter circuit, the method comprising, providing a first MOSFET transistor (112, paragraph 0027) and a second MOSFET transistor (118, paragraph 0025) coupled in series between the input node and the output node; providing a controller (116) comprising an output terminal for controlling the first and second MOSFET transistors ;providing a current limiter element (106) coupled in parallel with the second MOSFET transistor; providing a delay for delaying switching on of the second MOSFET transistor for a time period after the first MOSFET transistor is switched on (paragraph 0031); switching on the first MOSFET transistor during powering up of the power supply source, such that current flows between the input node and the output node via the current limiter element; and switching on the second MOSFET transistor after the time period, such that current flows between the input node and the output node, bypassing the current limiter element (paragraphs 0047-0050).
Rizzo does not teach that the delay is a delay circuit.
Hodge, Jr., in Figure 3, teaches an inrush current limiting circuit similar to Rizzo wherein a resistor (83) is provided to power to a load during startup and a controller sends a signal to bypass the resistor with a MOSFET (82) when it is determined that power is present at an input. The signal is delayed, allowing for the inrush current to resolve. It is further taught that the delay can be a dedicated delay circuit coupled with the output of the controller (paragraph 0022).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Rizzo with Hodge, Jr, by providing the delay of Rizzo as a delay circuit coupled to the output of the controller as taught by Hodge, Jr, for the purpose of providing a simple means to provide a delay that does not use processing power.
With regard to claims 11-13, 15 & 16, Rizzo in view of Hodge, JR discloses the method of claim 9, and further discloses that the step of providing the first MOSFET transistor and the second MOSFET transistor comprises, coupling an input terminal of the first MOSFET transistor to the input node; coupling an output terminal of the first MOSFET transistor to the input terminal of the second MOSFET transistor; and coupling an output terminal of the second MOSFET transistor to the output node (as seen in Fig. 1 of Rizzo) (re claim 11), wherein the step of providing the current limiter element comprises connecting a resistor in parallel with the input and output terminals of the second MOSFET transistor (Rizzo, paragraph 0033) (re claim 12), wherein the step of providing the controller comprises coupling an input terminal of the controller to the output node (through 108, 110, 112 & 126); and coupling the output terminal of the controller to respective gate terminals of the first and second MOSFET transistors (as seen in Fig. 1 of Rizzo) (re claim 13), wherein the time delay is a time period for the power supply capacitor to be sufficiently charged when current flows through the current limiter element (Rizzo, paragraph 0050) (re claim 15), wherein the first and second MOSFET transistors are PMOS transistors (while the reference does not specifically mention that the MOSFET transistors are PMOSFET transistors, the transistors would be either PMOSFET on NMOSFET devices and it would have been obvious to one of ordinary skill in the art at the time that the invention was filed to try either polarity of MOSFET as both choices are known equivalents of each other with similar results) (re claim 16).
Claims 6 & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Rizzo in view of Hodge, JR, as applied to claims 5 & 13 above, and further in view of Werback (US 2004/0169981).
With regard to claim 6, Rizzo in view of Hodge, JR, teaches the device of claim 5.
Rizzo in view of Hodge, JR, does not teach that the delay circuit comprises an RC delay element, said RC delay element comprising a delay resistor coupled between the controller output and the gate terminal of the second MOSFET transistor; and a capacitor coupled between the gate terminal of the second MOSFET transistor and the input terminal of the second MOSFET transistor
Werback, in Figure 2, teaches an inrush current limiter (19) similar to Rizzo wherein a delay circuit (209) allows a transistor (207) to be turned off during power up to allow an inrush current to flow through a resistor (203) and once a delay is met, the transistor (207) is turned on to bypass the resistor (paragraphs 0042 & 0043). It is further taught that the delay circuit comprises an RC delay element (211 & 213), said RC delay element comprising a delay resistor (213) coupled between ground and the gate terminal (210) of the MOSFET transistor; and a capacitor (211) coupled between the gate terminal of the second MOSFET transistor and the input terminal of the second MOSFET transistor (paragraph 0042).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Rizzo in view of Hodge, Jr. with Werback, by forming the delay circuit as taught by Werback, for the purpose of providing a simple well known circuit as the delay circuit that is low cost.
With regard to claim 14, Rizzo in view of Hodge, JR, teaches the method of claim 13.
Rizzo in view of Hodge, JR, does not teach that the step of providing the delay circuit comprises providing a delay resistor coupled between the output terminal of the controller and the gate terminal of the second MOSFET transistor; and providing a capacitor coupled between the gate terminal of the second MOSFET transistor and the input terminal of the second MOSFET transistor.
Werback, in Figure 2, teaches an inrush current limiter (19) similar to Rizzo wherein a delay circuit (209) allows a transistor (207) to be turned off during power up to allow an inrush current to flow through a resistor (203) and once a delay is met, the transistor (207) is turned on to bypass the resistor (paragraphs 0042 & 0043). It is further taught that the delay circuit comprises an RC delay element (211 & 213), said RC delay element comprising a delay resistor (213) coupled between ground and the gate terminal (210) of the MOSFET transistor; and a capacitor (211) coupled between the gate terminal of the second MOSFET transistor and the input terminal of the second MOSFET transistor (paragraph 0042).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Rizzo in view of Hodge, Jr. with Werback, by forming the delay circuit as taught by Werback, for the purpose of providing a simple well-known circuit as the delay circuit that is low cost.
Allowable Subject Matter
Claims 2 & 10 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a current limiter circuit comprising all the features as recited in the claims and in combination with prior to switching on the first MOSFET transistor, the controller is further configured to maintain the first MOSFET transistor and the second MOSFET transistor in respective off states for an initial time period, such that current flows from a body diode of the first MOSFET transistor to the output node via the current limiter element.
Claim 10 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a method comprising all the features as recited in the claims and in combination with prior to switching on the first MOSFET transistor, maintaining the first MOSFET transistor and the second MOSFET transistor in respective off states for an initial time period, such that current flows from a body diode of the first MOSFET transistor to the output node via the current limiter element.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Brooks (US 8,464,078) and Chen (US 2014/0084893) teach inrush current limiters that share similarities with Applicant’s invention.
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/Scott Bauer/Primary Examiner, Art Unit 2838
