DETAILED ACTION
This office action is in response to the application filed on January 22, 2025. Claims 1- 23 were cancelled. Claims 24-43 were added. Accordingly, Claims 24 – 43 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. GB2210742.9, filed on July 22, 2022.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on January 22, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The use of the trademark “Vulkan API” has been noted in this application as improper. It should be capitalized wherever it appears and be accompanied by the generic terminology.
Although the use of trademarks is permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as trademarks.
Claim Objections
In Claim 27, it recites the limitation “the main processor instructs the coprocessor using a Vulkan APL”. The Examiner has interpreted “the main processor instructs the coprocessor using a Vulkan APL” to mean “the main processor instructs the coprocessor using a Vulkan [[APL]] API”, as there appears to be is a typographical error (See disclosure Par. [0035] PG Pub).
In Claims 37 - 39, they recite the limitation “synchronisation primitives”. The Examiner has interpreted “synchronisation primitives” to mean “[[synchronisation]] synchronization primitives”, as there appears to be is a typographical error.
In Claim 27, it recites the limitation “the encoding process creates an encoded bitstream in accordance with MPEGS Part 2 LCEVC standard”. The Examiner has interpreted “the encoding process creates an encoded bitstream in accordance with MPEGS Part 2 LCEVC standard” to mean “the encoding process creates an encoded bitstream in accordance with [[MPEGS]] MPEG5 Part 2 LCEVC standard”, as there appears to be is a typographical error (See disclosure Par. [0032] PG Pub).
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 27 and 40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 27, it contains the trademark/trade name Vulkan API. Where a trademark or trade name is used in a claim as a limitation to identify or describe a particular material or product, the claim does not comply with the requirements of 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. See Ex parte Simpson, 218 USPQ 1020 (Bd. App. 1982). The claim scope is uncertain since the trademark or trade name cannot be used properly to identify any particular material or product. A trademark or trade name is used to identify a source of goods, and not the goods themselves. Thus, a trademark or trade name does not identify or describe the goods associated with the trademark or trade name. In the present case, the trademark/trade name is used to identify/describe the way the main processor instructs the coprocessor and, accordingly, the identification/description is indefinite.
Regarding Claim 40, it recites the limitations “relatively more complex discrete function” and “relatively less complex discrete functions”. This limitation is not clear. The term relatively more complex and relatively less complex are a relative terms which renders the claim indefinite. The terms are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 24 – 26, 28 – 32, 42 and 43 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Puri (US 2013/0077673 A1) referred to as Puri hereinafter.
Regarding Claim 24, Puri discloses a method of processing a video frame as part of an encoding process for video data (Figs. 1-5, Abstract, a method includes receiving data for compression at a first network device comprising an initial processing portion of a compression system, performing one or more processes to prepare the data for entropy encoding, compacting the data, and transmitting the compacted data to a second network device comprising an entropy encoding portion of the compression system), the method comprising:
configuring a coprocessor to process a video frame (Fig. 1, Par. [0021] the compression system is configured for hybrid GPU (graphics processing unit) (i.e. coprocessor)), the video frame comprising a plurality of blocks (Par. [0032] encoding of a video stream into a compressed bit stream using the modules shown in FIG. 3. A picture (i.e. video frame) is first partitioned into fixed-size macroblocks that each covers a rectangular picture area. Macroblocks are the basic building blocks of a standard for which the decoding process is specified that typically use 16.times.16 pixel macroblocks (i.e. plurality of blocks) as the principal processing unit.), in parallel using pipelining, the pipelining being configured according to a processing scheme which comprises a plurality of processes that each perform a discrete function of the encoding process on the plurality blocks of the video frame (Par. [0021] The initial processing portion 18 (i.e. processing scheme) of the encoding pipeline (i.e. pipelining) may be implemented on a GPU farm, where other processing (e.g., motion estimation (i.e. discrete function), transformation (i.e. discrete function), and quantization (i.e. discrete function)) (i.e. plurality of processes) is implemented on `parallel-friendly` (i.e. parallel) GPU hardware); and
processing the video frame at the coprocessor so that a plurality of the blocks are processed by a corresponding one of the plurality of processes in parallel (Par. [0021] the other processing (e.g., motion estimation, transformation, and quantization) is implemented on `parallel-friendly` GPU hardware);
wherein the plurality of processes are processes in the encoding process prior to entropy encoding (Fig. 1, Par. [0021] Compaction of the data transmitted from the initial processing portion 18 (i.e. prior to entropy encoding) to the entropy encoding portion 19 allows for each portion of the compression system to operate using independent processors, wherein the entropy encoding is implemented on a CPU).
Regarding Claim 25, Puri discloses claim 24. Puri further discloses wherein the coprocessor receives instructions from a main processor to perform the processing scheme (Par. [0021] hybrid (i.e. receives instructions from main processor) GPU (graphics processing unit)--CPU (central processing unit) implementation).
Regarding Claim 26, Puri discloses claim 25. Puri further discloses wherein the main processor is a central processing unit, CPU (Par. [0021] a CPU farm for entropy encoding), and the coprocessor is a graphical processing unit, GPU (Par. [0021] The initial processing portion 18 of the encoding pipeline may be implemented on a GPU farm).
Regarding Claim 28, Puri discloses claim 25. Puri further discloses wherein the coprocessor outputs the output from the final process of the processing scheme to the main processor for entropy encoding (Par. [0021] Compaction of the data transmitted from the initial processing portion 18 to the entropy encoding portion 19).
Regarding Claim 29, Puri discloses claim 24. Puri further discloses wherein the plurality of processes comprise one or more of: a convert process (Par. [0019] The compression system is configured to encode uncompressed input data (e.g., data stream, pixel data) into a compressed output bit stream (i.e. convert process)); an M-Filter process; a downsample process; a base encoder; a base decoder; a transport stream, TS complexity extraction process; a lookahead metrics extraction process; a perceptual analysis process; and an enhancement layer encoding process.
Regarding Claim 30, Puri discloses claim 29. Puri further discloses wherein the enhancement layer encoding process (It should be noted that claim 30 is dependent on claim 29 where “enhancement layer encoding process” is an optional limitation as recited by the term “comprise one or more of”. Accordingly, Claim 30 does not further limit claim 29, because one of the other alternatives is met) comprises one or more of the following processes: a first residual generating process to generate a first level of residual information; a second residual generating process to generate a second level of residual information; a temporal prediction process operating on the second level of residual information; one or more transform processes; and one or more quantization processes (Par. [0021] processing (e.g., motion estimation, transformation, and quantization) is implemented on `parallel-friendly` GPU hardware).
Regarding Claim 31, Puri discloses claim 30. Puri further discloses wherein the first residual generating process (It should be noted that claim 31 is dependent on claims 30 and 29 where “enhancement layer encoding process” and “a first residual generating process” are optional limitations as recited by the term “comprise one or more of”. Accordingly, Claim 31 does not further limit claims 30 or 29, because one of the other alternatives is met) comprises: a comparison of a downsampled version of a block with a base encoded and decoded version of the block (Par. [0021] processing (e.g., motion estimation, transformation, and quantization) is implemented on `parallel-friendly` GPU hardware).
Regarding Claim 32, Puri discloses claim 31. Puri further discloses wherein the second residual generating process (It should be noted that claim 32 is dependent on claims 31, 30 and 29 where “enhancement layer encoding process”, “a first residual generating process” and “second residual generating process” are optional limitations as recited by the term “comprise one or more of”. Accordingly, Claim 32 does not further limit claims 31, 30 or 29, because one of the other alternatives is met) comprises: a comparison of an input version of the block with an upsampled version of the base encoded and decoded version of the block corrected by the first level of residual information for that block (Par. [0021] processing (e.g., motion estimation, transformation, and quantization) is implemented on `parallel-friendly` GPU hardware).
Regarding Claim 42, Puri discloses a coprocessor for encoding video data (Fig. 1, Par. [0021] the compression system is configured for hybrid GPU (graphics processing unit) (i.e. coprocessor)), wherein the coprocessor is configured to perform the following:
process a video frame, the video frame comprising a plurality of blocks (Par. [0032] encoding of a video stream into a compressed bit stream using the modules shown in FIG. 3. A picture (i.e. video frame) is first partitioned into fixed-size macroblocks that each covers a rectangular picture area. Macroblocks are the basic building blocks of a standard for which the decoding process is specified that typically use 16.times.16 pixel macroblocks (i.e. plurality of blocks) as the principal processing unit), in parallel using pipelining, the pipelining being configured according to a processing scheme which comprises a plurality of processes that each perform a discrete function of the encoding process on the plurality blocks of the video frame (Par. [0021] The initial processing portion 18 (i.e. processing scheme) of the encoding pipeline (i.e. pipelining) may be implemented on a GPU farm, where other processing (e.g., motion estimation (i.e. discrete function), transformation (i.e. discrete function), and quantization (i.e. discrete function)) (i.e. plurality of processes) is implemented on `parallel-friendly` (i.e. parallel) GPU hardware); and
processing the video frame at the coprocessor so that a plurality of the blocks are processed by a corresponding one of the plurality of processes in parallel (Par. [0021] the other processing (e.g., motion estimation, transformation, and quantization) is implemented on `parallel-friendly` GPU hardware);
wherein the plurality of processes are processes in the encoding process prior to entropy encoding (Fig. 1, Par. [0021] Compaction of the data transmitted from the initial processing portion 18 (i.e. prior to entropy encoding) to the entropy encoding portion 19 allows for each portion of the compression system to operate using independent processors, wherein the entropy encoding is implemented on a CPU).
Claim 43 is a non-transitory computer-readable medium claim drawn to using the corresponds method claimed in claim 1. Therefore claim 43 corresponds to method claims1 and is rejected for the same reasons of anticipation as used above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 27 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Puri (US 2013/0077673 A1) in view of Fujimoto et al., (US 2018/0259762 A1) referred to as Fujimoto hereinafter.
Regarding Claim 27, Puri discloses claim 25. Puri does not specifically teach Vulkan APL. Therefore, Puri fails to explicitly teach the main processor instructs the coprocessor using a Vulkan API.
However, Fujimoto teaches the main processor instructs the coprocessor using a Vulkan API (Par. [0103], FIG. 12 schematically depicts one embodiment, where hardware for parallel processing 1205 is used by a kernel 1204, a type of parallel program, running on a GPU 1203 in the processing unit 1202 and implemented in a graphics programming language or API such as but not limited to CUDA, OpenCL, OpenGL, WebGL, Direct3D, Metal, Vulkan or Mantle).
References Puri and Fujimoto are considered to be analogous art because they relate to parallel processing. Therefore, it would be obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to specifying using Vulkan API as taught by Fujimoto in the invention of Puri. This modification would provide the ability of GPUs to rapidly perform image computation across the sequence of images to produce a processed representation of the sequence of images in real-time by dividing image processing tasks into many parallel processing operations that can run on hundreds or thousands of parallel processing units within a GPU concurrently (See Fujimoto, Par. [0103]).
Regarding Claim 40, Puri discloses claim 24. Puri does not specifically teach complex discrete functions. Therefore, Puri fails to explicitly teach processes of the processing scheme with relatively more complex discrete functions have greater assigned resources in the coprocessor than processes of the processing scheme with relatively less complex discrete functions.
However, Fujimoto teaches processes of the processing scheme with relatively more complex discrete functions have greater assigned resources in the coprocessor than processes of the processing scheme with relatively less complex discrete functions (Par. [0103] The use of a graphics programming language or API is advantageous because they expose the ability of GPUs to rapidly perform image computation (i.e. more complex discrete functions) across the sequence of images 1201 to produce a processed representation of the sequence of images 1206 in real-time by dividing image processing tasks into many parallel processing operations that can run on hundreds or thousands of parallel processing units within a GPU concurrently).
References Puri and Fujimoto are considered to be analogous art because they relate to parallel processing. Therefore, it would be obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to specifying using greater resources for more complex discrete functions as taught by Fujimoto in the invention of Puri. This modification would provide the ability of GPUs to rapidly perform image computation across the sequence of images to produce a processed representation of the sequence of images in real-time (See Fujimoto, Par. [0103]).
Claims 33 - 36 are rejected under 35 U.S.C. 103 as being unpatentable over Puri (US 2013/0077673 A1) in view of Tourapis et al., (US 2015/0249833 A1) referred to as Tourapis hereinafter.
Regarding Claim 33, Puri discloses claim 24. Puri does not specifically teach base encoder or decoder. Therefore, Puri fails to explicitly teach the processing scheme offloads a base encoder and base decoder operation to a dedicated base codec hardware, and outputs a downsampled version of a block to the dedicated base codec hardware and receives a base decoded version of the downsampled version after processing by the codec
However, Tourapis teaches the processing scheme (Fig. 8, Par. [0056] Encoding techniques) offloads a base encoder and base decoder operation to a dedicated base codec hardware (Par. [0056] a base encoder 820, a base decoder 830, Par. [0060] these components may be provided as hybrid systems that distribute functionality across dedicated hardware components), and outputs a downsampled version of a block to the dedicated base codec hardware and receives a base decoded version of the downsampled version after processing by the codec (Par. [0058] a base layer representation (i.e. downsampled version) corresponding to a lower representation of the signal, e.g. a lower dynamic range, resolution, frame-rate, bit-depth precision, chroma sampling, bitrate, etc., Fig. 8, base decoder 830 outputs based decoded version of downsampled version to enhancement encoder 860).
References Puri and Tourapis are considered to be analogous art because they relate to parallel processing. Therefore, it would be obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to specifying using a base encoder and base decoder as taught by Tourapis in the invention of Puri. This modification would provide encoding techniques for a scalable encoder environment (See Tourapis, Par. [0103]).
Regarding Claim 34, Puri in view of Tourapis teaches claim 33. Tourapis further teaches wherein the downsampled version is the lowest spatial resolution version in the encoding process (Par. [0058] a base layer representation (i.e. downsampled version) corresponding to a lower representation of the signal, e.g. a lower dynamic range, resolution (i.e. lowest spatial resolution version), frame-rate, bit-depth precision, chroma sampling, bitrate, etc.).
Regarding Claim 35, Puri in view of Tourapis teaches claim 33. Tourapis further teaches wherein the processing scheme performs forward complexity prediction on a given block while the base codec is working on the downsampled version of the given block (Par. [0058] the techniques described herein may be applied to multi-layer, e.g. scalable, video streams and workflows. For example, two (or more) signal representations may be generated: 1) a base layer representation (i.e. downsampled version) corresponding to a lower representation of the signal, e.g. a lower dynamic range, resolution, frame-rate, bit-depth precision, chroma sampling, bitrate, etc. 2) an enhancement layer representation (i.e. forward complexity prediction), which may be added to or considered in conjunction with the first base layer representation to enable a higher quality, resolution, bit-depth, chroma format, or dynamic range experience compared to that of the original).
Regarding Claim 36, Puri in view of Tourapis teaches claim 35. Tourapis further teaches wherein the forward complexity prediction comprises one or more of the following processes: a transport stream, TS complexity extraction process; a lookahead metrics extraction process; a perceptual analysis process (Par. [0024] other traits may be converted (and inverse converted) such as resolution, TF, linear data (e.g., floating point) to a fixed point representation using a particular, potentially perceptually optimized (i.e. perceptual analysis process), TF, etc.).
Claims 37 - 39 are rejected under 35 U.S.C. 103 as being unpatentable over Puri (US 2013/0077673 A1) in view of Hue (US 7,028,119 B2) referred to as Hue hereinafter.
Regarding Claim 37, Puri discloses claim 24. Puri does not specifically teach synchronization. Therefore, Puri fails to explicitly teach the processing scheme uses synchronization primitives to ensure that shared resources are assigned to only one process at a time.
However, Hue teaches the processing scheme uses synchronization primitives (Col. 11:49-55 The binary and mutual exclusion semaphores (i.e. synchronization primitives) are always in one of two states, empty or full. The binary semaphore can be used for mutual exclusion or synchronization) to ensure that shared resources are assigned to only one process at a time (Col. 11:24-27 protection mechanism in the code that allows for mutual exclusion (preventing one task from accessing data in use by another task)).
References Puri and Hue are considered to be analogous art because they relate to parallel processing. Therefore, it would be obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to specifying using synchronization primitives as taught by Hue in the invention of Puri. This modification would provide the fastest, most general-purpose semaphore (See Hue, Col. 11:40).
Regarding Claim 38, Puri in view of Hue teaches claim 37. Hue further teaches wherein the synchronization primitives are semaphores and wherein the semaphores are binary semaphores (Col. 11:54-56 The binary semaphore can be used for mutual exclusion or synchronization).
Regarding Claim 39, Puri in view of Hue teaches claim 37. Hue further teaches wherein earlier processes in the plurality of processes have a higher priority to any shared resources than later processes (Col. 11: 43-45 mutual exclusion (a special binary semaphore optimized or problems inherent in mutual exclusion, e.g., priority inheritance), the mutual exclusion semaphore contains a priority-inheritance algorithm, which assures that a task that owns a resource executes at the priority of the highest-priority task blocked on the resource relating to the semaphore), wherein the processing scheme uses a feedforward (Col. 1:57-60 The system also searches forward (i.e. feedforward) from the memory access through each of the plurality of threads for a deassert protection declaration, and identifies the potential race condition) when done method so that earlier processes in the plurality of processes signal to the next process when that earlier process is complete, and wherein the feedforward when done method uses the synchronization primitive (Col. 11:49-52 When a semaphore is taken, no other task is allowed to interrupt the task relating to the semaphore (e.g., by obtaining ownership of the semaphore) until the semaphore is given back (i.e. when done and complete)).
Claim 41 is rejected under 35 U.S.C. 103 as being unpatentable over Puri (US 2013/0077673 A1) in view of Grois et al. (US 2022/0103832 A1) referred to as Grois hereinafter.
Regarding Claim 41, Puri discloses claim 24. Puri further discloses the encoding process creates an encoded bitstream in accordance with standard (Par. [0037] compression system may also be used to encode data according to another standard, such as H.262, H.263, H.264, or other coding standard or format). Puri does not specifically teach MPEGS Part 2 LCEVC standard.
However, Grois teaches the encoding process creates an encoded bitstream in accordance with MPEGS Part 2 LCEVC standard (Fig. 1, Par. [0052] The encoder 104 may use similar methods when encoding content items according to any block-based hybrid video coding standards, such as H.264/MPEG-AVC, H.265/MPEG-HEVC, H.266/MPEG-VVC, MPEG-5 EVC, MPEG-5 LCEVC, AV1).
References Puri and Grois are considered to be analogous art because they relate to parallel processing. Therefore, it would be obvious to one possessing ordinary skill in the art before the effective filing date of the claimed invention to specifying MPEGS Part 2 LCEVC as taught by Grois in the invention of Puri. This modification would allow the encoder to use/implement parallel processing when encoding content items(See Grois, Par. [0052]).
Conclusion
The prior art references made of record are not relied upon but are considered pertinent to applicant's disclosure. CLUCAS et al. (US 2022/0086456 A1) teaches low latency communication systems and methods of encoding scheme that allows for parallel processing in the encoders and/or the decoders. MAKEEV et al. (US 2021/0084317 A1) teaches parallel processing and random access to a portion of data to be decoded and recreated implemented using separate FPGAs or on a GPU.
Any inquiry concerning this communication should be directed to SUSAN E HODGES whose telephone number is (571)270-0498. The Examiner can normally be reached on Monday - Friday from 8:00 am (EST) to 4:00 pm (EST).
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner's supervisor, Brian T. Pendleton, can be reached on (571) . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Susan E. Hodges/Primary Examiner, Art Unit 2425
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