DETAILED ACTION
This action responds to Application No. 18/998428, filed 01/24/2025, and to the preliminary amendment filed therewith.
At this point, claims 3-5 and 12-15 have been amended. New claims 16-20 have been added. Claims 1-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/25/2025, 02/05/2026, and 0512/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation “whether the first cache is the same as a cache currently exclusively holding the first data as recorded on a cache coherence node side” (e.g. claim 2, lines 5-6) is indefinite, for 2 reasons. First, it is unclear whether this limitation is intended to mean 1) determining whether the first cache exclusively owns the first data, 2) determining whether the first cache holds the same data that is exclusively owned by another cache, or 3) something else. Second, it is unclear what is meant by “on a cache coherence node side”; it seems to suggest there is some sort of dividing line between elements, but it is unclear what this is; moreover, assuming that the first cache and another cache on the cache coherence node side are on opposite “sides” of said dividing line, that would seem to preclude interpretation 1 above. Since Examiner is unable to determine the meaning of this limitation, it is indefinite.
Claims 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, for 2 reasons. First, re claim 8, the limitation “the first data written into the cache coherence node side” (e.g. claim 8, line 5-6) lacks sufficient antecedent basis in the claims. Second, re claims 8-9, as in claims 2 and 11 above, it is unclear what is meant by data being written into the cache coherence node side”, as it is unclear what the cache coherence side is.
Claims 16-17 and 19 are rejected as being dependent upon claim 2 above.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 16-20 or, alternatively, claims 1-2, 5-6, 8-11, 13-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mannava et al (US 2013/0042077 A1).
At the outset, it is noted that the entirety of claims 1-9 and 16-20 are all contingent upon “in response to receiving a write request from a first cache to write first data back to a memory”; as a method claim, it is thus subject to interpretation under MPEP § 2111.04(II), and the claim limitations are accordingly considered optional, as the condition of receiving the write request need not actually occur. Accordingly, claims 1-9 and 16-20 are rejected as being anticipated by Mannava, as it discloses multiple embodiments, including an embodiment in which the particular condition never occurs, and thus the contingent limitations are not required. Nevertheless, in the interest of furthering compact prosecution, Examiner has chosen to alternatively reject claims 1-9 and 16-20 by treating the contingent limitations as being positively recited; however, Examiner reserves the right to interpret claims 1-9 and 16-20 under the broadest reasonable interpretation afforded under MPEP § 2111.04(II).
Re claim 1, Mannava discloses the following:
A data processing method, comprising: in response to receiving a write request from a first cache to write first data back to a memory (Fig. 4a; ¶ 69). The home node (cache coherence node) receives a writeback request from a request node to write dirty data from its cache to memory;
writing, by a cache coherence node, the first data into the memory or discarding the first data (Fig. 4a; ¶ 72). It is noted that the broadest reasonable interpretation only requires one of these two options to be taught by the prior art; nevertheless, Mannava discloses both - the home node can either write the data or discard it;
wherein the write request carries the first data (¶ 58-59). The data itself may be transmitted along with the request;
the cache coherence node is configured to maintain coherence of data stored in a plurality of caches (Fig. 4a; ¶ 68-69). The home node corresponds to a cache coherence controller 60, and maintains coherence for caches of a plurality of requesting nodes;
and the plurality of caches comprise the first cache (Fig. 1). One of the requesting nodes comprises a cache (first cache);
after the writing, by the cache coherence node, the first data into the memory or discarding the data, returning, by the cache coherence node, a write response signal to the first cache to directly end a processing operation on the write request (Fig. 4a; ¶ 71-72). After the home node (cache coherence node) has issued the write along with the data to the memory controller for writing, and has responded to the read request from another node, the home node responds to the initiator device and its cache (first cache) to cause the first cache to mark its data as shared clean and complete the writeback (processing operation). It is noted that Applicant has not explicitly defined what it means to “directly end” an operation; Accordingly, Examiner interprets completing an operation as “directly ending” it.
Mannava discloses a plurality of embodiments; accordingly, while the above claim limitations may appear in more than one embodiment, it would nonetheless have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) combine these elements into a common embodiment, as it would be merely making the embodiments integral (MPEP § 2144.04(V)(B)).
Re claim 2, Mannava discloses the method of claim 1, and further discloses that in response to receiving the write request from the first cache to write the first data back to the memory, the writing, by the cache coherence node, the first memory into the memory or discarding the first data, comprises: in response to receiving the write request from the first cache to write the first data back to the memory, determining, by the cache coherence node, whether the first cache is the same as a cache currently exclusively holding the first data as recorded on a cache coherence node side; and in response to determining that the first cache is the same as the cache currently exclusively holding the first data as recorded on the cache coherence node side, writing, by the cache coherence node, the first data into the memory (¶ 69). This limitation is indefinite, as noted above. Examiner interprets it to mean that when it is determined that the data is exclusively owned by the first cache, the writeback is performed. Mannava discloses that the state of the data is initially unique, meaning it is the only local copy (exclusively holding), and in response, the process of performing the writeback is performed.
Re claim 5, Mannava discloses the method of claim 1, and further discloses the following:
in response to receiving a read request from a second cache for first data and determining that the first data is in an exclusive state or a shared state in the first cache as recorded by a cache coherence node side, initiating, by the cache coherence node, a monitor signal to the first cache (Fig. 4a; ¶ 69). In response to receiving a read request from another request node containing another cache (second cache), the home node (cache coherence node) issues a snoop (monitor signal) to the first requesting node containing the first cache;
in response to receiving, by the first cache, the monitor signal after initiating the write request, returning, by the first cache, a monitor response carrying the first data to the cache coherence node in response to the monitor signal (¶ 71). In response to the snoop, the first requesting node (first cache) sends a snoop response carrying the data to the home node (cache coherence node).
Re claim 6, Mannava discloses the method of claim 5, and further discloses
that in response to receiving the monitor response, returning, by the cache coherence node, the first data to the second cache; and (Fig. 4a; ¶ 71). In response to the home node receiving the snoop response, the home node (cache coherence node) returns the data to the second request node (second cache);
after receiving the first data, returning, by the second cache, a message to the cache coherence node indicating that the first data has been received to end the read request (Fig. 4a; ¶ 71). The home node (cache coherence node) receives a response from the second request node (second cache).
Re claim 8, Mannava discloses the method of claim 6, and further discloses that after the writing, by the cache coherence node, the first data into the memory or discarding the first data, the returning, by the cache coherence node, the write response signal to the first cache to directly end the processing operation on the write request, comprises: after receiving the message, discarding, by the cache coherence node, the first data written into the cache coherence node side by the write request, and returning the write response signal to the first cache to directly end the processing operation on the write request (¶ 71-72). The cache coherence node may drop (discard) the data, as well as returning the write response to the requesting node (first cache) to complete the writeback (directly end the processing operation).
Re claim 9, Mannava discloses the method of claim 8, and further discloses that after receiving the message, the discarding, by the cache coherence node, the first data written into the cache node side by the write request, comprises: in response to determining that the first data written into the cache coherence node side by the write request is invalid data after receiving the message, discarding, by the cache coherence node, the first data written into the cache coherence node side by the write request (¶ 33 and 72). If the data is invalid, then it will not be written (¶ 33), and may be dropped (discarded) (¶ 72).
Re claims 10-11 and 13, Mannava discloses the methods of claims 1-2 and 5 above, respectively; accordingly, they also disclose devices implementing those methods, as in claims 10-11 and 13, respectively (see Mannova, claim 1).
Re claim 14, Mannava discloses the method of claim 14; accordingly, it also discloses an apparatus configured to execute that method (see Mannova, claim 1). Furthermore, Mannova discloses a memory, configured to store computer-executable instructions; and a processor, configured to execute the computer-executable instructions (¶ 49). The system contains a processor to execute requests (computer-readable instructions) as well as a cache (memory) which may generate requests (computer-readable instructions).
Re claim 15, Mannava discloses the method of claim 14; accordingly, it also discloses a storage medium storing instructions implementing that method (¶ 49). See claim 14 above.
Re claim 19, the claim is directed to the same subject matter as claim 5, but is dependent upon claim 2 rather than claim 1. Accordingly, claim 19 is rejected for the same reasons noted above in claim 5.
Claims 3, 12, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mannava in view of Fujiwara et al (US 6298418 B1)
Re claim 3, Mannava discloses the method of claim 1; however, while Mannava discloses a response from the memory when it can be guaranteed that the memory will accept the writeback (¶ 71-72), it does not explicitly disclose sending a response when the data has actually completed writing. Accordingly, Examiner has provided Fujiwara.
Fujiwara discloses that after the writing, by the cache coherence node, the first data into the memory or discarding the first data, the returning, by the cache coherence node, the write response signal to the first cache to directly end the processing operation on the write request, comprises: after the writing, by the cache coherence node, the first data into the memory, returning, by the memory, a write response to the cache coherence node indicating that the first data has been written into the memory; and in response to receiving the write response from the memory indicating that the first data has been written into the memory, returning, by the cache coherency node, the write response signal to the first cache indicating that the first data has been written back to the memory, to directly end the processing operation on the write request (Fig. 1; Abstract). After a writeback to the memory is complete, the memory returns a complete response to the cache coherency check transceiver (cache coherency node), which in turn returns the write complete notification to the processor module which includes a cache (first cache), to indicate that the writeback is complete.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the cache coherency of Mannava to send a completion acknowledgement for the writeback upon actual completion of the writeback, as opposed to acceptance of the write command from the memory, because it would be applying a known technique to improve a similar method in the same way. Mannava discloses cache coherency. Fujiwara also discloses cache coherency, which has been improved in a similar way to the claimed invention, to send an acknowledgement once the writeback is actually complete. It would have been obvious to modify the cache coherency of Mannava to send an acknowledgement after writeback is complete, as in Fujiwara, because it would yield the predictable improvement of guaranteeing not just that the memory has accepted the write, but that it has actually written it, thus improving data reliability (preventing, for instance, data loss from a power outage after the acknowledgement from the memory but before the data is actually written).
Re claim 12, Mannava and Fujiwara disclose the method of claim 3; accordingly, they also disclose a device implementing that method, as in claim 12 (see Mannava, claim 1).
Re claim 16, the claim is directed to the same subject matter as claim 3, but is dependent upon claim 2 rather than claim 1. Accordingly, claim 16 is rejected for the same reasons noted above in claim 2.
Re claim 20, the claim is directed to the same subject matter as claim 5, but is dependent upon claim 3 rather than claim 1. Accordingly, claim 20 is rejected for the same reasons noted above in claim 5.
Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mannava in view of Wang (US 2017/0242797 A1).
Re claim 4, Mannava discloses the method of claim 1, but does not explicitly disclose that after the writing, the cache coherence node sets a data state to invalid, shared, or exclusive.
Wang discloses that after the writing, by the cache coherence node, the first data into the memory, setting, by the cache coherence node, a data state of the first cache to an invalid state, a shared state, or an exclusive state, wherein the invalid state indicates that the first cache does not cache the first data, the shared state indicates that the first cache and other cache both cache the first data, and the exclusive state indicates that only the first cache caches the first data (¶ 18). After a writeback (after the writing), the cache controller (cache coherence node) sets the state of the cache line to be “exclusive”. This is one of shared, invalid, and exclusive. All of these are part of the specified MESI protocol, and in the MASI protocol, invalid means that the cache line is not valid (i.e. the cache doesn’t cache the data), shared indicates that multiple caches have the data, and exclusive means that only one cache has the data.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the MESI protocol of Wang into the cache coherence of Mannava, because it would be applying a known technique to improve a similar method in the same way. Mannava discloses cache coherence. Wang also discloses cache coherence, which has been improved in a similar way to the claimed invention, to manage cache coherency using a MESI protocol. It would have been obvious to utilize the MESI protocol of Wang in the cache coherence of Mannava, because utilizing MESI would yield the predictable improvement of signaling to other caches/processors whether valid data exists in the cache location as well as in other caches.
Re claim 17, the claim is directed to the same subject matter as claim 4, but is dependent upon claim 2 rather than claim 1. Accordingly, claim 17 is rejected for the same reasons noted above in claim 4.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Mannava in view of Serebrin et al (US 2012/0144128 A1).
Re claim 7, Mannava discloses the method of claim 6, and further discloses in response to receiving the monitor response, the returning, by the cache coherence node, the first data to the second cache, comprises: in response to receiving the monitor response, returning, by the cache coherence node, the first data to the second cache (¶ 71), but does not explicitly disclose setting the data state to an exclusive state.
Serebrin discloses returning, by the cache coherence node, the first data to the second cache, and setting a data state of the second cache to an exclusive state, wherein the exclusive state indicates that only the second cache caches the first data (¶ 38). In response to a cache associated with a processor acquiring a read/write lock for data (returning the data from the cache coherence mechanisms (cache coherence node)), the data state of the second cache is set to exclusive such that no other core may read the cache line or cause them to be modified (thus all other copies are invalid).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the cache reading of Mannava to allow the requesting cache to acquire an exclusive read/write lock, as in Serebrin, because Serebrin suggests that this would allow for the instructions to be performed atomically to guarantee forward progress (¶ 37-38).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Mannava in view of Fujiwara, further in view of Wang
Re claim 18, the claim is directed to the same subject matter as claim 4, but is dependent upon claim 3 rather than claim 1. Accordingly, claim 18 is rejected for the same reasons noted above in claim 4.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the MESI protocol of Wang (combined with Fujiwara) into the cache coherence of Mannava, because it would be applying a known technique to improve a similar method in the same way. Mannava (combined with Fujiwara) discloses cache coherence. Wang also discloses cache coherence, which has been improved in a similar way to the claimed invention, to manage cache coherency using a MESI protocol. It would have been obvious to utilize the MESI protocol of Wang in the cache coherence of Mannava (combined with Fujiwara), because utilizing MESI would yield the predictable improvement of signaling to other caches/processors whether valid data exists in the cache location as well as in other caches.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Niell et al (2016/0378701 A1). Discloses completion responses for cache coherence over a fabric (¶ 48).
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/CRAIG S GOLDSCHMIDT/ Primary Examiner, Art Unit 2132
