DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-11 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 01/27/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites the limitations “the value” in line 8 of the claim, “the gate of the power transistor” in line 12 of the claim, “the input” in lines 14-15 of the claim, “the absence” in line 17 of the claim, and “the presence” in line 19 of the claim. This appears to mean “a value”, “a gate of the power transistor”, “an input”, “and absence”, and “a presence”, respectively. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: Claim 2 recites the limitation “the high-impedance state” 9-10 of the claim. This appears to mean “a high-impedance state”. Appropriate correction is required.
Claim 5 is objected to because of the following informalities: Claim 5 recites the limitations “the switching durations” in line 4 of the claim, “the evolution” in line 6 of the claim, and “the monitoring circuit” in line 13 of the claim. This appears to mean “switching durations”, “evolution” in line 6 of the claim, and “the circuit for monitoring”, respectively. Appropriate correction is required.
Claim 7 is objected to because of the following informalities: Claim 7 recites the limitations “the sixth resistor” and “the second output of the second push-pull circuit” in lines 4-5 of the claim. There is no antecedent basis for these limitations when the claim depends on claim 2, however if the claim depends on claim 6, these limitations would have proper antecedent basis. For the purposes of examination, claim 7 will be interpreted as depending upon claim 6 in order to obviate the antecedent basis issues. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: Claim 8 recites the limitations “the evolution of the current” in line 5 of the claim, “the monitoring circuit” in line 9 of the claim, “the control and protection device” in lines 9-10 of the claim, “a permanent leakage current” in line 12 of the claim, “the control and protection device” in lines 13-14, and “a monitoring circuit” in line 14 of the claim. This appears to mean “an evolution of a current”, “a monitoring circuit”, “the device”, “the permanent leakage current”, “the device”, and “the monitoring circuit”, respectively. Appropriate correction is required.
Claim 9 is objected to because of the following informalities: Claim 9 recites the limitation “the high-impedance state” in line 9-10 of the claim, “the terminals of the seventh resistor” in line 15 of the claim, and “the terminals of the eighth resistor” in line 15 of the claim. This appears to mean “a high-impedance state”, “terminals of the seventh resistor”, and “terminals of the eighth resistor”, respectively. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: Claim 10 recites the limitation “and at least one control and the device” in line 2 of the claim. This appears to mean “and the device”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The terms "high reference voltage" and “low reference voltage” in claim 1 are relative terms which render the claim indefinite. The terms "high" and “low” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitations "high reference voltage” and “low reference voltage” have been rendered indefinite by the use of the terms “high” and “low” because without a reference, any reference voltage can be explained as high or low. For the purposes of examination, the examiner has interpreted "high reference voltage" to be a reference voltage above the “low reference voltage” and “low reference voltage” to therefore be a reference voltage below the “high reference voltage”.
Claims 10 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term "several" in claim 10 is a relative term which renders the claim indefinite. The term "several" is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation "several power transistors” has been rendered indefinite by the use of the term “several” because without a reference, any number over one can be explained as several. For the purposes of examination, the examiner has interpreted "several power transistors" to be “two or more power transistors”. Claim 11 is rejected based on its dependency on claim 10.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelley et al. U.S. Patent Application 2010/0283515 (hereinafter “Kelley”) and further in view of Kwon U.S. Patent Application 2021/0293874 (hereinafter “Kwon”).
Regarding claim 1, Kelley teaches a device (refer to fig.3) for controlling a power transistor (i.e. JFET)(fig.3), comprising at least: - a nominal switching circuit of the power transistor (i.e. switches S1 and S3, and resistors R2 and R3)(fig.3), configured to control a nominal switching of the power transistor from a conducting state into a non-conducting state (refer to t1)(fig.10)(refer also to [0064]), hold the power transistor in the non-conducting state (refer to t3)(fig.10)(refer also to [0064]), and a nominal switching of the power transistor from the non-conducting state into the conducting state (refer to t1 and t2)(fig.10)(refer also to [0064]); - a circuit (i.e. switch S2 and resistor R1)(fig.3), configured to hold the power transistor in the conducting state (refer to [0060]); - a control circuit (refer to Vin)(fig.3)(refer also to [0063] and claim 8) configured to deliver control signals at the input of the nominal switching circuit (refer to Vin)(fig.3)(refer also to [0063] and claim 8); however, Kelley does not teach the device for protecting the power transistor, wherein the circuit is a short-circuit detecting circuit further configured to detect an increase in the value of the voltage VGS of the power transistor above a value of a high reference voltage, or a drop in the value of the voltage VGS below a value of a low reference voltage, which are representative of a short-circuit of the power transistor; - a protection circuit, configured to discharge the gate of the power transistor after detection of a short-circuit of the power transistor; wherein the control circuit is a measurement and control circuit further configured to deliver control signals at the input of the short-circuit detection circuit and the protection circuit such that: in the absence of a detected short-circuit, an input of the protection circuit coupled to the gate of the power transistor is set in a high-impedance state; in the presence of a detected short-circuit, outputs of the nominal switching circuit and the short-circuit detection circuit coupled to the gate of the power transistor are each set in a high-impedance state. However, Kwon teaches the device for protecting the power transistor (refer to fault handling circuit 104)(fig.1), wherein the circuit is a short-circuit detecting circuit (refer to figs. 4 and 8 and [0072] and [0073]) further configured to detect an increase in the value of the voltage VGS of the power transistor above a value of a high reference voltage, or a drop in the value of the voltage VGS below a value of a low reference voltage, which are representative of a short-circuit of the power transistor (refer to comparator 846)(fig.8)(refer also to [0072] and [0073]); - a protection circuit (refer to figs.10 and 11), configured to discharge the gate of the power transistor after detection of a short-circuit of the power transistor (refer to [0081]); wherein the control circuit is a measurement and control circuit (refer to figs.4 and 5) further configured to deliver control signals at the input of the short-circuit detection circuit and the protection circuit such that: in the absence of a detected short-circuit, an input of the protection circuit coupled to the gate of the power transistor is set in a high-impedance state (refer to [0030]); in the presence of a detected short-circuit, outputs of the nominal switching circuit and the short-circuit detection circuit coupled to the gate of the power transistor are each set in a high-impedance state (refer to [0030]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kelley to include the protection of Kwon to provide the advantage of protecting the power transistor from damage due to faults.
Regarding claim 2, Kelley and Kwon teach the device according to claim 1, wherein the nominal switching circuit includes at least:- a first push-pull circuit (i.e. Kelley switches S1 and S3 and resistors R2 and R3)(fig.3) comprising a first output (i.e. Kelley first output in the figure below)(fig.3) configured to be coupled to the gate of the power transistor through a first resistor (i.e. Kelley resistor R2)(fig.3)(refer also to Kwon resistor 112)(fig.1), and a second output (i.e. Kelley second output in the figure below)(fig.3) configured to be coupled to the gate of the power transistor through at least one second resistor (i.e. Kelley resistor R3)(fig.3)(refer also to Kwon resistor 114)(fig.1); - a first voltage level conversion circuit (refer to pulse generator and inverter in the figure below)(fig.3)(refer also to Kwon Pre-Driver 102)(fig.1) comprising at least one first control input (i.e. Kwon FLT and pre-driver 102)(fig.1) on which a nominal switching control signal is intended to be applied from the measurement and control circuit (implicit), a second control input (i.e. Kwon INP and pre-driver 102)(fig.1) on which a signal for setting in the high-impedance state the first and second outputs of the first push-pull circuit is intended to be applied from the measurement and control circuit (implicit), and configured to deliver, on outputs coupled to control inputs of the first push-pull circuit, signals for controlling the first push-pull circuit (implicit)(refer to Kelley figure 3)(refer also to Kwon Gon and Goff)(fig.1).
PNG
media_image1.png
360
495
media_image1.png
Greyscale
Regarding claim 4, Kelley and Kwon teach the device according to claim 1,wherein the protection circuit includes a second switch (i.e. Kwon S2 in the figure below)(fig.11) comprising an input (i.e. I1 in the figure below)(fig.11) configured to be coupled to the gate of the transistor power through a fourth resistor (i.e. fourth resistor in the figure below)(fig.11), and an output (i.e. O1 in the figure below)(fig.11) configured to be coupled to a reference electrical potential (implicit).
PNG
media_image2.png
247
504
media_image2.png
Greyscale
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelley and Kwon as applied to claim 1 above, and further in view of Park et al. European Patent Document EP 3076549 A1 (hereinafter “Park”).
Regarding claim 3, Kelley and Kwon teach the device according to claim 1,wherein the short-circuit detection circuit includes at least: - a first switch (refer to Kwon gate voltage clamp circuit)(fig.11) comprising an output (i.e. Kwon I2 in the figure above)(fig.11) configured to be coupled to the gate of the power transistor through a third resistor (i.e. Kwon R3 in the figure above)(fig.11); - a second voltage level conversion circuit (i.e. Kwon flip-flop 1058)(fig.10) comprising at least one control input on which a short-circuit detection control signal is intended to be applied from the measurement and control circuit (refer to Kwon Set input and FOCHSF signal)(fig.10), and configured to deliver, on an output coupled to a control input of the first switch, a signal for controlling the first switch (implicit)(refer to Kwon FLT)(figs.10 and 11); - a first comparator circuit (i.e. Kwon comparator 846)(fig.8) configured to deliver, on an input of the measurement and control circuit (refer to Kwon VGE_SC)(fig.8), a signal representative of a difference between the value of the voltage VGS of the power transistor and the value of the high reference voltage (refer to Kwon FFUL)(fig.8); however, they do not teach - a second comparator circuit configured to deliver, on an input of the measurement and control circuit, a signal representative of a difference between the value of the voltage VGS of the power transistor and the value of the low reference voltage. However, Park teaches - a second comparator circuit (i.e. CMP1)(fig.1) configured to deliver, on an input of the measurement and control circuit, a signal representative of a difference between the value of the voltage VGS of the power transistor (implicit)(refer to fig.1) and the value of the low reference voltage (i.e. voltage V1)(fig.1)(refer also to fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kelley and Kwon to include the second comparator of Park to provide the advantage of improving the accuracy of the short circuit detection.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelley and Kwon as applied to claim 1 above, and further in view of Tavernier et al. U.S. Patent Application 2017/0192049 (hereinafter “Tavernier”).
Regarding claim 8, Kelley and Kwon teach the device according to claim 1; however, they do not teach the device further including a circuit for detecting a permanent leakage current through the gate of the power transistor configured to: - set the power transistor in the conducting or non-conducting state, and - measure the evolution of the current on the gate of the power transistor, and wherein the measurement and control circuit is configured to deliver control signals such that: - when the power transistor is controlled by the nominal switching circuit or by the short-circuit detection circuit, or by the monitoring circuit when the control and protection device includes such a circuit, outputs of the permanent leakage current detection circuit are each set in a high-impedance state; - upon detection of a permanent leakage current, the outputs of the nominal switching circuit, the short-circuit detection circuit, and the monitoring circuit when the control and protection device includes such a monitoring circuit, and the input of the protection circuit are each set in a high-impedance state. However, Tavernier teaches the device further including a circuit for detecting a permanent leakage current (i.e. detection circuit 31)(fig.1)(refer also to [0044]) through the gate of the power transistor configured to: - set the power transistor in the conducting or non-conducting state (refer to abstract), and - measure the evolution of the current on the gate of the power transistor (refer to abstract), and wherein the measurement and control circuit is configured to deliver control signals (refer to abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kelley and Kwon to include the permanent leakage current detection of Park to provide the advantage of increasing the accuracy of the short-circuit detection. However, Kelley, Kwon, and Tavernier do not teach delivering the control signals such that: - when the power transistor is controlled by the nominal switching circuit or by the short-circuit detection circuit, or by the monitoring circuit when the control and protection device includes such a circuit, outputs of the permanent leakage current detection circuit are each set in a high-impedance state; - upon detection of a permanent leakage current, the outputs of the nominal switching circuit, the short-circuit detection circuit, and the monitoring circuit when the control and protection device includes such a monitoring circuit, and the input of the protection circuit are each set in a high-impedance state. Kwon teaches setting the currently unused switches to high-impedance state when other switches are operating (refer to Kwon [0030]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kelley, Kwon, and Tavernier to apply the high impedance state of Kwon to any currently unused switches to provide the advantage of minimizing leakage of the transistor. Therefore, Kelley, Kwon, and Tavernier teach delivering the control signals such that: - when the power transistor is controlled by the nominal switching circuit or by the short-circuit detection circuit, or by the monitoring circuit when the control and protection device includes such a circuit, outputs of the permanent leakage current detection circuit are each set in a high-impedance state (refer to Kwon [0030]); - upon detection of a permanent leakage current, the outputs of the nominal switching circuit, the short-circuit detection circuit, and the monitoring circuit when the control and protection device includes such a monitoring circuit, and the input of the protection circuit are each set in a high-impedance state (refer to Kwon [0030]).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelley and Kwon as applied to claim 1 above, and further in view of Schmidt U.S. Patent Application 2015/0002187 (hereinafter “Schmidt”).
Regarding claim 10, Kelley and Kwon teach a power converter or module (refer to Kelley [0084]); comprising the device according to claim 1 (refer to the rejection of claim 1); however, they do not teach several power transistors and the device coupled to one of said power transistors. However, Schmidt teaches several power transistors (refer to converter 2)(fig.1) and the device coupled to one of said power transistors (refer to control logic 6)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power converter or module of Kelley and Kwon to include the several power transistors of Schmidt to provide the advantage of using a converter capable of converting power from a source into the proper form for a load, such as converting power from a battery into three-phase power for a three-phase motor (refer to Schmidt [0026]).
Regarding claim 11, Kelley, Kwon, and Schmidt teach an aircraft (refer to Schmidt [0026]) comprising at least one power converter or module according to claim 10 (refer the rejection of claim 10 above).
Allowable Subject Matter
Claims 5-7 and 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action, overcome the minor informalities set forth in this Office action, and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 5-7 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 5, especially a circuit for monitoring a state-of-health of a gate oxide of the power transistor configured to: - control a slow switching of the power transistor in which the switching durations are longer than those of the nominal switching, and - measure the evolution of the voltage VGS of the power transistor during a slow switching of the power transistor, and - calculate a duration of a so-called Miller plateau during the evolution of the measured voltage VGS, and wherein the measurement and control circuit is configured to deliver control signals such that: - when the power transistor is controlled by the nominal switching circuit or by the short-circuit detection circuit, outputs of the monitoring circuit configured to be coupled to the gate of the power transistor are each set in a high-impedance state; - during a slow switching of the power transistor, the outputs of the nominal switching circuit and the short-circuit detection circuit and the input of the protection circuit are each set in a high-impedance state. Claims 6 and 7 are indicated as containing allowable subject matter based on their dependency on claim 5.
Claims 9 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 9, especially wherein the permanent leakage current detection circuit includes at least: - a third push-pull circuit comprising a first output configured to be coupled to the gate of the power transistor through a seventh resistor, a second output configured to be coupled to the gate of the power transistor through an eighth resistor;- a fourth voltage level conversion circuit comprising at least one first control input on which a permanent leakage current detection control signal is intended to be applied from the measurement and control circuit, a second control input on which a signal for setting in the high-impedance state the first and second outputs of the third push-pull circuit is intended to be applied from the measurement and control circuit, and configured to deliver, on outputs coupled to control inputs of the third push-pull circuit, signals for controlling the third push-pull circuit;- a circuit for measuring the gate current of the power transistor, which inputs are coupled to the terminals of the seventh resistor and to the terminals of the eighth resistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN J COMBER/Primary Examiner, Art Unit 2838
