DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending in this application.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/23/2024 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zeng et al. U.S. Patent Application 2020/0294837 (hereinafter “Zeng”).
Regarding claim 1, Zeng teaches a wafer placement table (i.e. structure 200)(fig.4) comprising: a first conductive layer (i.e. first conductive layer in the figure below)(fig.4); a second conductive layer (i.e. second conductive layer in the figure below)(fig.4) different in height from the first conductive layer (implicit)(refer to fig.4); and a connector (i.e. connector in the figure below)(fig.4) that electrically connect the first conductive layer and the second conductive layer (implicit)(refer to fig.4), inside a ceramic plate (i.e. ceramic plate 21)(fig.4) having a wafer placement surface on its upper surface (refer to recessed supporting portion 211)(fig.4), wherein the first conductive layer, the second conductive layer and the connector are formed in a seamless one-piece structure (i.e. curved-surface circuit)(fig.4).
PNG
media_image1.png
531
671
media_image1.png
Greyscale
Regarding claim 2, Zeng teaches the wafer placement table according to Claim 1, further comprising: a main RF electrode (i.e. plasma control circuit 24)(fig.4) provided inside the ceramic plate (implicit)(refer to fig.4); a sub-RF electrode as the first conductive layer (refer to first conductive layer in the figure above)(fig.4) provided on an outer circumferential side of the main RF electrode (implicit)(refer to fig.4); a jumper as the second conductive layer (refer to second conducive layer in the figure above)(fig.4) provided below the sub-RF electrode (implicit)(refer to fig.4 above); a main RF electrode rod (i.e. main rod in the figure above)(fig.4), electrically connected to the main RF electrode (implicit)(refer to [0056]); and a sub-RF electrode rod (i.e. sub rod in the figure above)(fig.4) electrically connected to the jumper (implicit)(refer to [0056]).
Regarding claim 5, Zeng teaches the wafer placement table according to Claim 2, wherein a boundary between the jumper and the connector is located inside the main RF electrode in a plan view (implicit)(refer to fig.4 above).
Regarding claim 8, Zeng teaches the wafer placement table according to Claim 2, further comprising a tubular shaft (i.e. tube 26)(fig.4) connected to a lower surface of the ceramic plate (implicit)(refer to fig.4)(refer also to [0056]), wherein the main RF electrode rod and the sub-RF electrode rod are disposed in an internal space of the tubular shaft (refer to [0056]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zeng as applied to claim 1 above, and further in view of Endo Japanese Patent Document JP 3311812 B2 (hereinafter “Endo”).
Regarding claim 6, Zeng teaches the wafer placement table according to Claim 2; however, Zeng does not teach wherein a boundary between the jumper and the connector is a valley fold line in a plan view, and a boundary between the sub-RF electrode and the connector is a mountain fold line in a plan view. However, Endo teaches wherein a boundary between the jumper and the connector is a valley fold line in a plan view (refer to central portion 15a and valley in the figure below)(fig.2), and a boundary between the sub-RF electrode and the connector is a mountain fold line in a plan view (refer to peripheral portion 15b and mountain in the figure below)(fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the wafer placement table of Zeng to include the shape of the electrode of Endo to provide the advantage of better controlling the plasma density distribution.
PNG
media_image2.png
395
485
media_image2.png
Greyscale
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zeng as applied to claim 1 above, and further in view of Inoue Japanese Patent Document JP 2004-179364 A (hereinafter “Inoue”).
Regarding claim 9, Zeng teaches the wafer placement table according to Claim 1; however, Zeng does not teach wherein the one-piece structure is made of a conductive mesh. However, Inoue teaches wherein the one-piece structure is made of a conductive mesh (refer to [0041]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the wafer placement table of Zeng to include the conductive mesh of Inoue to provide the advantage of simplifying manufacture of the wafer placement table (refer to [0041]).
Allowable Subject Matter
Claims 3, 4, 7, and 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 3 and 10 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 3, especially wherein the jumper includes a horizontal conductor provided at a central portion of the ceramic plate; and a plurality of first conductive wires that horizontally extend from an outer edge of the conductor and have rotational symmetry, the connector is formed by a plurality of second conductive wires that respectively extend diagonally upward from the plurality of first conductive wires, and the sub-RF electrode is a ring-shaped set in which horizontal conductive arc portions respectively contiguous to the plurality of second conductive wires are arranged in a circumferential direction. Claim 10 is indicated as containing allowable subject matter based on its dependency on claim 3. Claim 4 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 4, especially wherein the jumper is a horizontal conductor provided at a central portion of the ceramic plate, the connector is formed by a plurality of conductive wires that extend diagonally upward from an outer edge of the conductor and have rotational symmetry, and the sub-RF electrode is a ring-shaped set in which horizontal conductive arc portions respectively contiguous to the plurality of conductive wires are arranged in a circumferential direction. Claim 7 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 7, especially wherein a boundary between the jumper and the connector is a valley fold line in a plan view, and a boundary between the sub-RF electrode and the connector is a valley fold line in a plan view.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN J COMBER/Primary Examiner, Art Unit 2838
Prosecution Insights