CTNF 18/999,082 CTNF 91698 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections 07-29-01 AIA Claim 16 is objected to because of the following informalities: The examiner suggest amending the claim limitation “the firs” to recite “the first” to fix the spelling error and provide better quality . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 11 and 14-15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Hosur et al. (US Pub No. 2021/0328789) . Regarding independent claim 11 , Hosur teaches an encrypting method of a memory system including an electrical circuit and a memory device including a plurality of areas, the method comprising: receiving a plurality of encryption requests including a first encryption request for first data stored in a first area of the plurality of areas and a second encryption request for second data stored in a second area of the plurality of areas ( Hosur, page 2, paragraphs 0017, 0021-0023 & and page 3, paragraphs 0032-0033; database server with encryption module including a key cache; store data for multiple tenants; receive write request from multiple tenants ); transmitting the second encryption request to the memory device in response to a determination that a first encryption variable for the first area is not stored in a cache memory of the electrical circuit and a second encryption variable for the second area is stored in the cache memory ( Hosur, page 2, paragraphs 0017-0020 & 0027-0029 and page 4, paragraphs 0051-0052; allow writes from other tenants when there is no key for tenant A ); and generating the first encryption variable while encrypting the second data received from the memory device based on the second encryption variable ( Hosur, page 2, paragraphs 0017-0019 & 0029 and page 4, paragraphs 0045-0047; key management system generate new encryption key and send new encryption key back to cache; while encryption module still allow encryption & writes for other tenant data based on the encryption key for that tenant ), encrypting the first data based on the generated first encryption variable ( Hosur, pages 2-3, paragraphs 0029 & 0033; continue writes for tenant A when the new key arrives in the cache ). Regarding claim 14 , Hosur teaches the method wherein the encrypting of the first data further incudes: transmitting the first encryption request to the memory device in response to a determination that the first encryption variable is generated; receiving the first data from the memory device; and encrypting the first data received from the memory device based on the first encryption variable after the encryption of the second data is completed ( Hosur, page 2, paragraphs 0017-0020 & 0027-0029 and pages 3-4, paragraphs 0042-0043 ). Regarding claim 15 , Hosur teaches the method further comprising: receiving, after the first encryption request and the second encryption request, a third encryption request for third data stored in a third area of the plurality of areas; and encrypting one of the first data or the third data based on a determination of whether the first encryption is generated, such that the first data is encrypted based on the first encryption variable at a time point when encryption for the second area is completed and in response to a determination that the first encryption variable is generated and the third data stored in the third area is encrypted based on a third encryption variable stored in the cache memory at a time point when the encryption for the second area is completed and in response to a determination that the first encryption variable is not generated ( Hosur, page 2, paragraphs 0017-0019 & 0027-0029, pages 3-4, paragraphs 0042-0043 and page 4, paragraphs 0051-0052; inherent the same process will apply; allows encryption and write request for other tenants ) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3, 9-10 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hosur et al. (US Pub No. 2021/0328789) in view of Choi et al. (US Pub No. 2011/0055176) . Regarding independent claim 1 , Hosur teaches an electronic circuit configured to communicate with a memory device, comprising: an encryption circuit including a cache memory storing an encryption variable for some of a plurality of areas of the memory device, and configured to receive a plurality of encryption requests including a first encryption request for first data stored in a first area of the plurality of areas of the memory device and a second encryption request for second data stored in a second area of the plurality of areas of the memory device ( Hosur, page 2, paragraphs 0017, 0021-0023 & and page 3, paragraphs 0032-0033; database server with encryption module including a key cache; store data for multiple tenants; receive write request from multiple tenants ); transmit the second encryption request to the memory device when a first encryption variable for the first area is not stored in the cache memory and a second encryption variable for the second area is stored in the cache memory ( Hosur, page 2, paragraphs 0017-0020 & 0027-0029 and page 4, paragraphs 0051-0052; allow writes from other tenants when there is no key for tenant A ); and a variable generation circuit configured to generate the first encryption variable while the encryption circuit encrypts the second data received from the memory device based on the second encryption variable in response to the second encryption request ( Hosur, page 2, paragraph 0019 & 0029 and page 4, paragraphs 0045-0047; key management system generate new encryption key and send new encryption key back to cache; while encryption module still allow encryption & writes for other tenant data ), transmits the first encryption request to the memory device in response to a determination that the first encryption variable is generated ( Hosur, page 3, paragraph 0029; continue writes for tenant A when the new key arrives in the cache ). Hosur disclose blocking write operation for a tenant when a key is invalidated in the cache, while accepting other writes operation from other tenant ( Hosur, pages 2-3, paragraphs 0017-0020 & 0029 ), however does not explicitly teach a scheduler configured to transmit the second encryption request to the memory device; and wherein the scheduler transmits the first encryption request to the memory device in response to a determination that the first encryption variable is generated. Choi teaches a scheduler configured to transmit the second encryption request to the memory device ( Choi, page 4, paragraph 0115 and page 6, paragraphs 0175-0177; scheduler transmit content to request encoding based on content being in received status & changed content status ); and wherein the scheduler transmits the first encryption request to the memory device in response to a determination that the first encryption variable is generated ( Choi, page 4, paragraph 0115 and page 6, paragraphs 0175-0177; scheduler transmit content to request encoding based on content being in received status & changed content status ). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Hosur with teaching of Choi to include a scheduler to provide the advantage of improving content deliver ( Choi, page 1, paragraph 0003 ). Regarding claim 2 , Hosur in view of Choi teaches the electronic circuit wherein the encryption circuit is configured to: receive the second data from the memory device; and encrypt the second data based on the second encryption variable ( Hosur, page 2, paragraphs 0017-0020 & 0027-0029 and pages 3-4, paragraphs 0042-0043 ). Regarding claim 3 , Hosur in view of Choi teaches the electronic circuit wherein the encryption circuit is configured to: transmit a first generation request to the variable generation circuit when the first encryption variable is not stored in the cache memory; acquire the first encryption variable from the variable generation circuit; receive the first data from the memory device; and encrypt the first data based on the first encryption variable in response to a determination that the encryption of the second data is completed ( Hosur, page 2, paragraphs 0017-0020 & 0027-0029 and pages 3-4, paragraphs 0042-0043 & 0045-0047; key management system generate new encryption key and send new encryption key back to cache; while encryption module still allow encryption & writes for other tenant data ). Regarding claim 9 , Hosur teaches the electronic circuit wherein, when the encryption circuit receives a third encryption request for a third area following the first encryption request and the second encryption request, and a third encryption variable for the third area is stored in the cache memory, the scheduler is configured to transmit one of the first encryption request or the third encryption request based on a determination of whether the first encryption is generated such that the first encryption request is transmitted to the memory device at a time point when encryption of the second area is completed and the first encryption variable is generated; and the third encryption request is transmitted to the memory device at a time point when the encryption of the second area is completed and the first encryption variable is not generate ( Hosur, page 2, paragraphs 0017-0019 & 0027-0029, pages 3-4, paragraphs 0042-0043 and page 4, paragraphs 0051-0052; inherent the same process will apply; allows encryption and write request for other tenants ). Regarding claim 10 , Hosur teaches the electronic circuit wherein, when the encryption circuit receives a third encryption request for a third area following the first encryption request and the second encryption request, and a third encryption variable for the third area is not stored in the cache memory, the variable generation circuit is configured to generate the third encryption variable, and the scheduler is configured to transmit the third encryption request to the memory device in response to a determination that an encryption of the first area is completed and the third encryption variable is generated ( Hosur, page 2, paragraphs 0017- 0019 & 0027-0029, pages 3-4, paragraphs 0042-0043 and page 4, paragraphs 0051-0052; inherent the same process will apply; allows encryption and write request for other tenants ). Regarding independent claim 16 , Hosur teaches an electronic circuit configured to communicate with a memory device including a plurality of areas, comprising: an encryption circuit including a cache memory storing an encryption variable for some of a plurality of areas, and configured to receive a first encryption request for first data stored in a first area of the plurality of areas and a second encryption request for second data stored in a second area of the plurality of areas ( Hosur, page 2, paragraphs 0017, 0021-0023 & and page 3, paragraphs 0032-0033; database server with encryption module including a key cache; store data for multiple tenants; receive write request from multiple tenants ); transmit the second encryption request to the memory device when a first encryption variable for the first area is not stored in the cache memory and a second encryption variable for the second area is stored in the cache memory ( Hosur, page 2, paragraphs 0017-0020 & 0027-0029 and page 4, paragraphs 0051-0052; allow writes from other tenants when there is no key for tenant A ); and a variable generation circuit configured to receive the first encryption variable from the memory device, wherein the electronic circuit is configured such that the encryption circuit encrypts the second data received from the memory device based on the second encryption variable in response to the second encryption request while the variable acquisition circuit receives the firs encryption variable ( Hosur, page 2, paragraph 0019 & 0029 and page 4, paragraphs 0045-0047; key management system generate new encryption key and send new encryption key back to cache; while encryption module still allow encryption & writes for other tenant data ), the first encryption request to the memory device in response to a determination that the first encryption variable is received by the variable acquisition circuit ( Hosur, page 3, paragraph 0029; continue writes for tenant A when the new key arrives in the cache ). Hosur disclose blocking write operation for a tenant when a key is invalidated in the cache, while accepting other writes operation from other tenant ( Hosur, pages 2-3, paragraphs 0017-0020 & 0029 ), however does not explicitly teach a scheduler configured to transmit the second encryption request to the memory device; and wherein the scheduler is configured to transmit the first encryption request to the memory device in response to a determination that the first encryption variable is received by the variable acquisition circuit. Choi teaches a scheduler configured to transmit the second encryption request to the memory device ( Choi, page 4, paragraph 0115 and page 6, paragraphs 0175-0177; scheduler transmit content to request encoding based on content being in received status & changed content status ); and wherein the scheduler is configured to transmit the first encryption request to the memory device in response to a determination that the first encryption variable is received by the variable acquisition circuit ( Choi, page 4, paragraph 0115 and page 6, paragraphs 0175-0177; scheduler transmit content to request encoding based on content being in received status & changed content status ). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Hosur with teaching of Choi to include a scheduler to provide the advantage of improving content deliver ( Choi, page 1, paragraph 0003 ). Regarding claim 17 , Hosur in view of Choi teaches the electronic circuit wherein the encryption circuit is configured to: receive the second data from the memory device; and encrypt the second data based on the second encryption variable ( Hosur, page 2, paragraphs 0017-0020 & 0027-0029 and pages 3-4, paragraphs 0042-0043 ). Regarding claim 18 , Hosur in view of Choi teaches the electronic circuit wherein the encryption circuit is configured to: transmit first acquisition request to the variable acquisition circuit in response to a determination that the first encryption variable is not stored in the cache memory; acquire the first encryption variable through the variable acquisition circuit; receive the first data from the memory device in response to a determination that encryption of the second data is completed; and encrypt the first data based on the first encryption variable and the first data ( Hosur, page 2, paragraphs 0017-0020 & 0027-0029 and pages 3-4, paragraphs 0042-0043 & 0045-0047; key management system generate new encryption key and send new encryption key back to cache; while encryption module still allow encryption & writes for other tenant data ). Regarding claim 19 , Hosur in view of Choi teaches each and every claim limitation of claim 16, however Choi teaches the electronic circuit wherein the variable acquisition circuit is configured to transmit a first preparation signal to the scheduler in response to a determination that the first encryption variable is acquired from the memory device, and wherein the scheduler is configured to transmit the first encryption request to the memory device in response to the first preparation signal ( Choi, page 4, paragraph 0115, page 5, paragraph 0152, and page 6, paragraphs 0175-0177; scheduler receives status information from syndication portal; syndication portal generate key ). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Hosur with teaching of Choi to include a scheduler to provide the advantage of improving content deliver ( Choi, page 1, paragraph 0003 ). Regarding claim 20 , Hosur in view of Choi teaches the electronic circuit wherein, while the encryption circuit encrypts the second data, the variable acquisition circuit is configured to: transmit a first variable request to the memory device; and acquire the first encryption variable from the memory device ( Hosur, page 2, paragraph 0019 & 0029 and page 4, paragraphs 0045-0047; key management system generate new encryption key and send new encryption key back to cache; while encryption module still allow encryption & writes for other tenant data ) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4-8 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Statement for Indicating Allowable Subject Matter 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art KANG et al. (US Pub No. 2019/0121749) discloses electronic apparatus that writes encrypted data includes a first memory; a second memory configured to update encryption information including address information indicating a write location on the first memory and a parameter for use in encryption when data is encrypted and written to the first memory, and store the updated encryption information; an encryption and decryption unit configured to encrypt the data, based on the encryption information; and a processor configured to control the encrypted data to be written to the first memory, thereby increasing a safety level. ( KANG, Abstract ) and HONG et al. (US Pub No. 2018/0173654) discloses memory device includes a memory cell region including a plurality of memory cells; a memory cell controller configured to control read and write operation for the memory cell region; one or more NDP engines configured to perform a near data processing (NDP) operation for the memory cell region; a command buffer configured to store an NDP command transmitted from a host; and an engine scheduler configured to schedule the NDP operation for the one or more NDP engines according to the NDP command. ( HONG, Abstract ), however, the prior art taken alone or in combination does not teach or suggest “ wherein the variable generation circuit is configured to: acquire first metadata for the first area from the memory device in response to the first generation request; and generate the first encryption variable for the first area based on the first metadata ” (as recited in claims 4 & 11) and “ wherein the scheduler includes: a request buffer configured to store encryption requests, from among the plurality of encryption requests, received through the encryption circuit; a wait buffer configured to store encryption requests, from among the plurality of encryption requests, of which an encryption variable for an area requesting encryption is not stored in the cache memory; and an output circuit configured to sequentially output the encryption requests stored in the request buffer and the wait buffer to the memory device ” (as recited in claim 7), in combination with the remaining claim limitations . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAQUEAL D WADE whose telephone number is (571)270-0357. The examiner can normally be reached M-F 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Thiaw can be reached at 571-270-1138. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAQUEAL D WADE-WRIGHT/Primary Examiner, Art Unit 2407 Application/Control Number: 18/999,082 Page 2 Art Unit: 2407 Application/Control Number: 18/999,082 Page 3 Art Unit: 2407 Application/Control Number: 18/999,082 Page 4 Art Unit: 2407 Application/Control Number: 18/999,082 Page 5 Art Unit: 2407 Application/Control Number: 18/999,082 Page 6 Art Unit: 2407 Application/Control Number: 18/999,082 Page 7 Art Unit: 2407 Application/Control Number: 18/999,082 Page 8 Art Unit: 2407 Application/Control Number: 18/999,082 Page 9 Art Unit: 2407 Application/Control Number: 18/999,082 Page 10 Art Unit: 2407 Application/Control Number: 18/999,082 Page 11 Art Unit: 2407 Application/Control Number: 18/999,082 Page 12 Art Unit: 2407 Application/Control Number: 18/999,082 Page 13 Art Unit: 2407 Application/Control Number: 18/999,082 Page 14 Art Unit: 2407
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