DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 23 December, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitations are: “data flow control unit” in claim 1 line 5 and claim 18 line 5, and “data movement unit” in claim 2 line 3. The limitations:
(A) utilize a generic placeholder (data control/movement “unit”)
(B) are modified by functional language (both contain purely functional description (“for performing control”, “for copying” )
(C) are not modified with sufficient structure (neither limitation describes physical/structural characteristics of a device which embodies the “units”)
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-10 and 18-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claims contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 1 and 18 contain the limitation of a “data flow control unit”. As addressed in the interpretation under 35 U.S.C. 112(f), the limitation is given the broadest reasonable interpretation in light of the specification. However, the “data flow control unit” is not described using any structural language in the specification, meaning it is unclear to one of ordinary skill in the art how to implement the claimed unit.
Claim 2 contains the limitation of a “data movement unit”. As addressed in the interpretation under 35 U.S.C. 112(f), the limitation is given the broadest reasonable interpretation in light of the specification. However, the “data movement unit” is not described using any structural language in the specification, meaning it is unclear to one of ordinary skill in the art how to implement the claimed unit.
Claims 3-10 and 19-20 depend from claims 1 and 18, respectively, and as such are seen to contain the same deficiencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Gu et al (U.S. Patent Pub. No. 2023/0205729), hereinafter referred to as Gu, in view of Wu et al (U.S. Patent No. 10,346,093), hereinafter referred to as Wu, and Hariharan et al (U.S. Patent No. 11,748,253), hereinafter referred to as Hariharan.
In regard to claim 1, Gu teaches an artificial neural network processing accelerator based on a systolic array (Title, ¶ 0056 SNCPU may be configured as accelerator), comprising: a processing element array (¶ 0005, lines 1-4); internal memory for storing input/output data of the processing element array (Fig. 2 SRAM/Cache, L2 Memory).
Gu does not explicitly teach a data flow control unit, however Wu teaches a data flow control unit for performing control to deliver an input tensor and weight data from the internal memory to the processing element array (Column 2, line 52 to Column 3, line 11: memory controller inside accelerator controls input of tensors from internal RAM to processing array) in each operation cycle (Column 10, lines 8-14 RAM circuits operate per cycle to provide data to processing elements) and to store an output tensor from the processing element array in the internal memory (Column 12, lines 1-10 as an example data may be output to RAM circuits from PEs which would include tensors in functional operation). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Wu in order to dynamically store and retrieve data from the processing array and to deliver a desired bandwidth to a processing array using flexible multi-ported memory (Column 3, line 66 to Column 4, line 2).
The previously cited references do not explicitly teach memory banks corresponding to processing rows with an interface for rearranging connections, however Hariharan discloses an embodiment wherein the internal memory includes N memory banks respectively corresponding to N rows of the processing element array (Column 16, lines 20-24 disclose a memory subsystem 1004 in accelerator 1002 (Fig. 10) that has a memory bank to serve each connected client, wherein each row of the processing array 1010 may be a separate client), and further includes a rearrangement interface for connecting input/output between the N rows of the processing element array and the N memory banks (Column 16, lines 36-41 memory subsystem 1004 includes control logic to manage memory banks and interfaces with processing array 1010 in Fig. 10; the initial disclosure of Hariharan is directed toward independent access of separate memory banks, including IC devices accessing different banks at different times as shown in Fig. 2B; Column 16, lines 41-45 disclose that banks may be hardwired in some implementations (with no drawbacks to either configuration listed), which implies to one of ordinary skill in the art that they may also not be hardwired i.e. reconnectable (see MPEP 2123 § I, "reference disclosing optional inclusion of a particular component (for ex. hardwired connections vs some shared interface) teaches compositions that both do and do not contain that element")). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Hariharan in order to access different memory banks at different times and to increase the efficiency of a neural processing accelerator by using independently accessible memory banks (Column 16, lines 1-6).
As for claim 5, the previously cited references teach the accelerator of claim 1. Additionally, Wu teaches an embodiment wherein the data flow control unit generates an internal memory address value corresponding to data to be read from the internal memory in each operation cycle and generates an internal memory address value to which output data from the processing element array is to be written. Column 2, lines 59-64 disclose that the memory controller for the RAM circuits sends read and write (i.e. input and output) addresses to the RAM circuits for operations, achieving the claimed limitation.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Wu, Hariharan, and Redfern et al (U.S. Patent Pub. No. 2018/0246669), hereinafter referred to as Redfern. The previously cited references teach the accelerator of claim 1. The previously cited references do not teach the remaining limitations of claim 2. However, Redfern teaches a data movement unit for copying artificial neural network input data and weight data from external memory to the internal memory. Redfern ¶ 0005, lines 2-4 disclose a matrix transfer accelerator with a data transfer processor for transferring data to internal memory from an external memory. ¶ 0063, lines 4-6 disclose using the disclosed techniques for neural network processing. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Redfern in order to efficiently access external data and implement systems for efficient data movement when processing CNN data (¶ 0065, lines 1-6).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Wu, Hariharan, and Nama et al (U.S. Patent No. 11,263,170), hereinafter referred to as Nama. The previously cited references teach the accelerator of claim 5. They do not explicitly teach the remaining limitations of claim 6. However, Nama teaches a configuration controller 195 attached to an array of processing and memory units 190 (see Fig. 1, see Fig. 2 for unit array diagram) which may be configured with input neural network data files from a compiler on a host (Column 7, lines 9-11 application may be a compiled CNN; lines 34-43 configuration files (i.e. register files) are loaded onto memory and processors). A person of ordinary skill in the art could implement this teaching in the previously referenced RAM controller of Wu which generates and delivers addresses to processor memory banks on a clock cycle (see rejections of claims 1 and 5), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Nama in order to deploy specific neural network targets and to benefit from increased efficiency in distributed computing with accelerator units (Column 48, lines 53-65).
Allowable Subject Matter
Claims 3-4 and 7-10 are objected to as being dependent upon a rejected base claim, but in the event that the rejection under 35 USC 112 is overcome, would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 includes the limitation wherein the rearrangement interface includes N-1 multiplexers, a k-th multiplexer inputs an input tensor output from at least one of a k-th memory bank, or a (k+1)-th memory bank, or a combination thereof to a k-th row of the processing element array, and an input tensor output from an N-th memory bank is input to an N-th row of the processing element array. Claim 4 includes a very similar limitation applied to outputs of the processing array. Multiple prior art references disclose the use of multiplexers for connecting memory banks to processing elements, and the most similar reference Huynh et al (U.S. Patent Pub. No. 2021/0158132) was found to teach an input selector 730 for a processing element array 710 (see Fig. 7) having multiplexers for connection (¶ 0103). However, no reference was found to teach the entirety of the claimed limitations (e.g. the configuration of multiplexers in relation to memory banks and processor rows), in whole or in part.
Given the above findings, claims 3-4 would be found allowable over prior art if rewritten to address objections.
Claim 7 includes the limitation wherein the register file includes a start address of an input tensor, a loop offset, information about a loop for generating a Y coordinate, and information about a slice height of the input tensor. Reference Temam et al (U.S. Patent Pub. No. 2018/0365561, hereinafter referred to as Temam) discloses a tensor traversal unit for providing data including loop offsets for generating address values (¶ 0032), but does not teach files having information relating to tensor slices or coordinates. Therefore, no reference was found to teach the entirety of the claimed limitations, in whole or in part.
Given the above findings, claim 7 would be found allowable over prior art if rewritten to address objections. Claims 8-10 would be found allowable by virtue of dependence on claim 7.
Claims 11-17 are allowed.
Claim 11 includes the limitations generating an initial address value for internal memory based on a nested loop; extracting a Y coordinate of a tensor based on information about a loop for generating a Y coordinate; generating a final address value for the internal memory based on a result of comparing the extracted Y coordinate with a slice height of the tensor; and connecting input/output between N rows of a processing element array and N memory banks through a rearrangement interface based on the final address value. Previously cited reference Temam was found to be the most similar prior art to these limitations, but as stated does not teach address generation based on tensor slices or coordinates. Therefore, no reference was found to teach the entirety of the claimed limitations, in whole or in part.
Given the above findings, claim 11 is found allowable over prior art. Claims 12-17 are found allowable by virtue of dependence on allowable claim 11.
Additionally, given the above findings regarding claim 11, claim 18 would be found allowable over prior art in the event that the rejection under 35 USC 112 is overcome because it contains the same allowable limitations as claim 11. Claims 19-20 would then be found allowable by virtue of dependence on claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
“An Agile Design Method for Reconfigurable Spatial Accelerators in Tensor Computation” discloses methods of manipulating tensors in neural network accelerators.
Lyuh et al (U.S. Patent Pub. No. 2022/0164192) discloses embodiments of processing element arrays similar to the instant application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139