DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Response to Arguments
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
Applicant argues: (1) Chen’s transposition is a continuously maintained mirror of the first register set, generated in response to a modification of that set, rather than a transposition performing during the loading of the matrix into the operations register [Remarks, pp. 6-7]; (2) Chen’s mirrored register arrangement places the transpose in the separate VMX set and not in the operations register [remarks, p. 7]; (3) claims 2, 9, 16 recite additional novel and non-obvious features [remarks, p. 8]; (4) claims 3, 4, 10, 11, 17, and 18 recite additional novel and non-obvious features [remarks, pp. 8-9]; (5) claims 7 and 14 recite additional novel and non-obvious features [remarks, p. 9].
The examiner respectfully disagrees with these arguments.
Regarding the first argument, the examiner notes that Chen stores a matrix in a first set of registers (described as MMX registers in Chen; col. 2, lines 34-36). The claimed invention then performs a transposition on said matrix during a loading of the matrix into an operations register of the processing unit. The examiner mapped the claimed “operations register” to Chen’s “second set of registers” (VMX register set) and according to Chen, the second set of registers store the transposed matrix data [Chen, col. 3, lines 15-34, “virtual MMX register set linked to the MMXTM register set”; “VMX register set 22 stores the transposed matrix data from the MMXTM register set”…”For example, the data from the first MMXTM register mm012 may be automatically stored in the low units of the VMX registers VM0 through VM7, the data from the second MMXTM register mm120 may be automatically stored in the second lowest units of the VMX registers, and so on.”] Applicant argues that Chen’s register update logic (e.g., update logic that updates the second set whenever any unit of any register in the MMX set is modified), is a continuously maintained mirror of the first register set rather than a transposition performed during loading, and therefore does not teach the claimed limitation [remarks, pp. 6-7]. However, the bolded portion of Chen explicitly discloses “performing a transposition operation during a loading of the matrix into an operations register.” Recalling that the examiner has mapped Chen’s second set of registers (VMX registers) to the claimed operations register, the data from the first MMXTM register mm012 may be automatically stored in the low units of the VMX registers VM0 through VM7, the data from the second MMXTM register mm120 may be automatically stored in the second lowest units of the VMX registers, and so on. The bolded portions of Chen emphasizes the transposition operation where the data from mm012 is stored in the low units of VMX registers VM0-VM7. The next row mm120 is then stored in the second lowest units of VMX registers. Chen illustrates an example of a transposed matrix [col. 2, lines 64-65, “transpose the 8x8 matrix as shown in FIG. 3], where the mm012 (of fig. 2) is stored in the low units of VM0 through VM7:
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86
475
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is stored in the low units as shown below.
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311
123
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.
The next row mm120 (of fig. 2) is then stored in the second lowest units of VMX registers as shown in fig. 3 here:
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31
478
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is stored as second lowest units a shown below.
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234
52
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Hence Chen explicitly discloses the claimed limitation of “performing a transposition operation during a loading of the matrix into an operations register of the processing unit” [Chen, col. 3, lines 15-34, “virtual MMX register set linked to the MMXTM register set”; “VMX register set 22 stores the transposed matrix data from the MMXTM register set”…”For example, the data from the first MMXTM register mm012 may be automatically stored in the low units of the VMX registers VM0 through VM7, the data from the second MMXTM register mm120 may be automatically stored in the second lowest units of the VMX registers, and so on.”]
The examiner acknowledges applicant’s remarks regarding Chen’s update logic, however the examiner notes that updating the second set of registers does not change the fact that data from the first MMXTM register mm012 may be automatically stored in the low units of the VMX registers VM0 through VM7, the data from the second MMXTM register mm120 may be automatically stored in the second lowest units of the VMX registers, and so on.
Regarding the second argument, the examiner cited Chen’s second set of registers as being equivalent to the claimed operations register [Non-Final Rejection, p. 3]. As explained above, Chen clearly discloses performing a transposition operation during loading of the matrix into the second set of registers, such that the second set of registers stores a copy of the transposed matrix.
Regarding the third argument, in regards to claims 2, 9, and 16, applicant has not provided specifically pointed out how the language of the claims patentably distinguishes themselves from the references. Therefore, the prior art rejection of claims 2, 9, and 16 is maintained.
Regarding the fourth argument, in regards to claims 3, 4, 10, 11, 17, and 18, applicant has not provided specifically pointed out how the language of the claims patentably distinguishes themselves from the references. Therefore, the prior art rejection of claims 3, 4, 10, 11, 17, and 18 is maintained.
Regarding the fifth argument, in regards to claims 7 and 14, applicant has not provided specifically pointed out how the language of the claims patentably distinguishes themselves from the references. Therefore, the prior art rejection of claims 7 and 14 is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, US 6625721 B1, in view of Gokhale et al (hereinafter Gokhale), US 20240385837 A1, and further in view of Thomas, US 20250284768 A1.
Referring to claims 1, 8, and 15, taking claim 1 as exemplary, Chen discloses a method comprising:
receiving, from a memory of a processing unit, a matrix [col. 1, lines 35-50, “a processor having a first set of registers, the first set storing a matrix of data”];
performing a transposition operation during a loading of the matrix into an operations register of the processing unit [col. 1, lines 35-50, “a second set of registers coupled to the first set, the second set storing a transposed copy of the matrix of data”; “transposing the matrix of data into a second set of registers”], and
storing the transposed matrix in the operations register of the processing unit [col. 1, lines 35-50, “a second set of registers coupled to the first set, the second set storing a transposed copy of the matrix of data”; “transposing the matrix of data into a second set of registers”].
Chen does not explicitly disclose the matrix having one of a row-major layout or a column-major layout.
However, Gokhale discloses the matrix having one of a row-major layout or a column-major layout [paragraph 45, “The matrix transpose unit 116 may be connected to the vector processing unit 112 or other registers in order to receive a source matrix for transposition. The received matrix may be transposed and then the transposed matrix is returned to the vector processing unit 112 or other registers from which the matrix was received. Alternatively, the matrix transpose unit 116 may pass the transposed matrix to a different destination, such as a matrix multiplication unit 114 or a different set of registers. In some examples, it may be possible for the registers themselves or other components positioned along a communication path between the vector processing unit 112 and the MXU 114 to function as the matrix transpose unit 116. In these examples, the received matrix can be transposed from either row-major or column-major format into the transposed matrix, meaning that pre-processing is not required in order to perform the transposition”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Gokhale in the method of Chen to implement, the matrix having one of a row-major layout or a column-major layout, in order to allow transpose operations to be performed more efficiently by avoiding data conflicts along the communication datapath of the matrix transpose unit. [Gokhale, paragraph 36].
The modified Chen does not explicitly disclose the matrix comprising data elements having a 6-bit floating-point (FP6) data format.
However, Thomas discloses the matrix comprising data elements having a 6-bit floating-point (FP6) data format [paragraph 96, “Matrix elements may be stored at different precisions depending on the particular implementation”; “In one embodiment, one or more 8-bit floating-point (FP8), 6-bit floating-point (FP6), and 4-bit floating-point (FP4) formats are supported”; paragraph 352, “matrix transposition can be performed via convert/transpose logic 3108A-3108D for input matrix A data via matrix A transpose circuitry 3108A-3108D and matrix B transpose circuitry 3113A-3113B”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Thomas in the method of the modified Chen to implement, the matrix comprising data elements having a 6-bit floating-point (FP6) data format, in order to ensure that the most efficient precision is used for different workloads [Thomas, paragraph 96].
Claim(s) 2, 9, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Gokhale, in view of Thomas, as applied to claims 1, 8, and 15 above, and further in view of Ramchandran, US 20040093479 A1.
Referring to claims 2, 9, and 16, taking claim 2 as exemplary, the modified Chen does not explicitly disclose the method of claim 1,
wherein the memory comprises a plurality of cache lines, wherein receiving the matrix comprises receiving one or more data elements that are partially stored across multiple cache lines of the plurality of cache lines, and wherein the transposition operation comprises:
caching at least some of the partially stored data elements, and
combining the cached at least some of the partially stored data elements with subsequently received data to complete the transposition operation.
However, Ramchandran discloses wherein the memory comprises a plurality of cache lines, wherein receiving the matrix comprises receiving one or more data elements that are partially stored across multiple cache lines of the plurality of cache lines [paragraph 54], and wherein the transposition operation comprises:
caching at least some of the partially stored data elements [paragraph 54], and
combining the cached at least some of the partially stored data elements with subsequently received data to complete the transposition operation [paragraph 54, “An embodiment of the distributed cache architecture having eight data buses and eight cache memories, each with eight cache lines, can efficiently transpose an 8x8 matrix. To transpose a matrix, a matrix row is read from local memory by the data address generators, and each element of the matrix row is transferred to a different data bus. Then, a burst mode operation is used to simultaneously transfer all of the row elements from their respective data buses into the corresponding cache lines of one of the cache memories. This process is repeated for the remaining rows of the matrix, with each row being stored in a different cache memory. Once this operation is completed, each cache memory contains a column of the transposed matrix”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Ramchandran, in the method of the modified Chen, to implement, wherein the memory comprises a plurality of cache lines, wherein receiving the matrix comprises receiving one or more data elements that are partially stored across multiple cache lines of the plurality of cache lines, and wherein the transposition operation comprises: caching at least some of the partially stored data elements, and combining the cached at least some of the partially stored data elements with subsequently received data to complete the transposition operation, in order to efficiently perform matrix operations for a wide variety of applications that offers fast performance and flexible configuration [Ramchandran, paragraph 40].
Claim(s) 3-4, 10-11, and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Gokhale, in view of Thomas, as applied to claims 1, 8, and 15 above, and further in view of Mantor, US 20180239606 A1.
Referring to claims 3, 10, and 17, taking claim 3 as exemplary, the modified Chen does not explicitly disclose the method of claim 1, wherein the operations register of the processing unit is one of a group that comprises a general-purpose register of the processing unit, a vector general-purpose register (VGPR) of the processing unit, or a tensor core of the processing unit.
However, Mantor discloses wherein the operations register of the processing unit is one of a group that comprises a general-purpose register of the processing unit, a vector general-purpose register (VGPR) of the processing unit [paragraph 28, fig. 2, GPU 200 with VGPRs 230], or a tensor core of the processing unit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Mantor, in the method of the modified Chen, to implement, wherein the operations register of the processing unit is one of a group that comprises a general-purpose register of the processing unit, a vector general-purpose register (VGPR) of the processing unit, or a tensor core of the processing unit, in order to schedule instructions with less of a challenge [Mantor, paragraph 3].
Referring to claims 4, 11, and 18, taking claim 4 as exemplary, the modified Chen discloses the method of claim 3, wherein the processing unit is a graphics processing unit (GPU), and wherein the operations register of the processing unit is a vector general-purpose register (VGPR) of the GPU [Mantor, fig. 2, VGPRs 230].
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Gokhale, in view of Thomas, as applied to claims 1 and 8 above, and further in view of Leven et al (hereinafter Leven), US 20190278596 A1.
Referring to claims 7 and 14, taking claim 7 as exemplary, the modified Chen does not explicitly disclose the method of claim 1, wherein performing the transposition operation comprises loading a subset of columns from the received matrix into respective continuous row segments of the transposed matrix in the operations register.
However, Leven discloses performing the transposition operation comprises loading a subset of columns from the received matrix into respective continuous row segments of the transposed matrix in the operations register [paragraph 145, “Programs typically store matrices in row-major or column-major order. Row-major order stores all the elements of a single row contiguously in memory. Column-major order stores all elements of a single column contiguously in memory”; “In a typical example, an index steps through columns on one array and rows of the other array. The streaming engine supports implicit matrix transposition with transposed streams”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Leven, in the method of the modified Chen, to implement, wherein performing the transposition operation comprises loading a subset of columns from the received matrix into respective continuous row segments of the transposed matrix in the operations register, in order to improve memory bandwidth and data scheduling [Leven, paragraph 49].
Allowable Subject Matter
Claims 5-6, 12-13, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the transposition operation comprises: retrieving a first subset of matrix data elements from memory during a first pass; retrieving a second subset of matrix data elements during a second pass; and combining the first subset and the second subset into the transposed matrix, in combination with other recited limitations in claim 5.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the transposition operation comprises interleaving alignment padding between two or more subsets of the data elements, in combination with other recited limitations in claim 6.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein to transpose the matrix includes to: retrieve a first subset of matrix data elements from memory during a first pass; retrieve a second subset of matrix data elements during a second pass; and combine the first subset and the second subset into the transposed matrix, in combination with other recited limitations in claim 12.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein to transpose the matrix comprises interleaving alignment padding between two or more subsets of the data elements, in combination with other recited limitations in claim 13.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the transposition operation comprises: retrieving a first subset of matrix data elements from memory during a first pass; retrieving a second subset of matrix data elements during a second pass; and combining the first subset and the second subset into the transposed matrix, in combination with other recited limitations in claim 19.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the transposition operation comprises interleaving alignment padding between two or more subsets of the data elements, in combination with other recited limitations in claim 20.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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