DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a) regarding claim 14:
In claim 14, line 8, the acronym “PI” is undefined and therefore indefinite.
In claim 14, lines 10-11, the limitation, “a second calculator configured to generate a first constant voltage by calculating the reference voltage and the feedback value,” is unclear and therefore indefinite. It is unclear how the calculator (e.g. 440 in Figure 21) is “calculating the reference voltage and feedback value” when those signals are inputs to the calculator. It is calculating a sum or difference of those signals?
b) regarding claim 19:
In claim 19, line 6, the acronym “PI” is undefined and therefore indefinite.
In claim 19, lines 8-9, the limitation, “a second calculator configured to generate a first constant voltage by calculating the reference voltage and the feedback value,” is unclear and therefore indefinite. It is unclear how the calculator (e.g. 440 in Figure 21) is “calculating the reference voltage and feedback value” when those signals are inputs to the calculator. It is calculating a sum or difference of those signals?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (KR 20240049143).
a) regarding claim 1:
Kim et al. discloses a pulse generator (Figure 4) comprising:
a first constant voltage generator (VS1) connected to a first voltage node (N1);
a second constant voltage generator (VS2) connected to a second voltage node (N2);
a first switch (SW1) connected between the first voltage node (N2) and a first node (node between SW1 and SW3);
a second switch (SW3) connected between the first node and a third node (N3);
a third switch (SW2) connected between the third node (N3) and a second node (node between SW2 and SW4);
a fourth switch (SW4) connected between the second node and the second voltage node (N2); and
a clamping circuit (D1 and D2) connected between at least one of the first node (node between SW1 and SW3 via SW1) and the second node (node between SW2 and SW4 via SW4) and an output node (Nout), and configured to reduce an overshoot of an output voltage (Vout) that is output through the third node and the output node (paragraphs [0062], [0067] and [0091]).
b) regarding claim 2:
Kim et al. discloses the pulse generator of claim 1, wherein the clamping circuit includes a first clamping diode (D1) connected between the first node (node between SW1 and SW3 via SW1) and the output node (Nout).
c) regarding claim 3:
Kim et al. discloses the pulse generator of claim 2, wherein the clamping circuit further includes a second clamping diode (D2) connected between the second node (node between SW2 and SW4 via SW4) and the output node (Nout).
d) regarding claim 4:
Kim et al. discloses the pulse generator of claim 1, further comprising:
a first diode (D3) connected between the first node (node between SW1 and SW3) and a ground; and
a second diode (D4) connected between the second node (node between SW2 and SW4) and the ground.
e) regarding claim 5:
Kim et al. discloses the pulse generator of claim 1, further comprising an inductor (L) connected between the third node (N3) and the output node (Nout).
f) regarding claim 6:
Kim et al. discloses the pulse generator of claim 5, further comprising a variable capacitor (C5 in Figure 7b) connected between the third node (N3) and the output node (Nout).
g) regarding claim 7:
Kim et al. discloses the pulse generator of claim 1, further comprising an LC network (L and C5 in Figure 7a) connected to the output node (Nout).
h) regarding claim 8:
Kim et al. discloses the pulse generator of claim 1, wherein in a first switching state, the first switch (SW1) and the second switch (SW3) are configured to be in an on state, and the third switch (SW2) and the fourth switch (SW4) are configured to be in an off state (Figure 6a),
in a second switching state, the first switch (SW1) and the second switch (SW3) are configured to be in an off state, and the third switch (SW2) and the fourth switch (SW4) are configured to be in an on state (Figure 6c), and
the pulse generator is configured to generate the output voltage by alternately switching between the first switching state and the second switching state (paragraphs [0060], [0073] and [0079]).
i) regarding claim 9:
Kim et al. discloses the pulse generator of claim 1, wherein in a first switching state, the first switch (SW1) and the second switch (SW3) are configured to be in an on state, and the third switch (SW2) and the fourth switch (SW4) are configured to be in an off state (Figure 6a),
in a second switching state, the second switch (SW3) and the third switch (SW2) are configured to be in an on state, and the first switch (SW1) and the fourth switch (SW4) are configured to be in an off state (Figure 6e), and
the pulse generator is configured to generate the output voltage by alternately switching between the first switching state and the second switching state (paragraph [0079]).
j) regarding claim 10:
Kim et al. discloses the pulse generator of claim 1, wherein in a first switching state, the first switch (SW1) and the second switch (SW3) are configured to be in an on state, and the third switch (SW2) and the fourth switch (SW4) configured to be are in an off state (Figure 6a),
in a second switching state, the second switch (SW3) and the third switch (SW2) are configured to be in an on state, and the first switch (SW1) and the fourth switch (SW4) are configured to be in an off state (Figure 6e),
in a third switching state, the first switch (SW1) and the second switch (SW3) are configured to be in an off state, and the third switch (SW2) and the fourth switch (SW4) are configured to be in an on state (Figure 6c), and
the pulse generator is configured to generate the output voltage by successively switching between the first switching state, the second switching state, the third switching state, and the second switching state (paragraph [0079]).
k) regarding claim 13:
Kim et al. discloses the pulse generator of claim 1, wherein in a first switching state, the first switch (SW1) and the second switch (SW3) are configured to be in an on state, and the third switch (SW2) and the fourth switch (SW4) are configured to be in an off state (Figure 6a),
in a second switching state, the first switch (SW1), the second switch (SW3), the third switch (SW2), and the fourth switch (SW4) are configured to be in an off state (Figure 6b or 6d),
in a third switching state, the second switch (SW3) and the third switch (SW2) are configured to be in an on state, and the first switch (SW1) and the fourth switch (SW4) are configured to be in an off state (Figure 6e), and
the pulse generator is configured to sequentially switch between the first switching state, the second switching state, and the third switching state (paragraph [0079]).
Allowable Subject Matter
Claims 15-18 and 20 are allowed.
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to disclose or make obvious a pulse generator, wherein in a second switching state, the first switch is configured to be in an on state, and the second switch, the third switch, and the fourth switch are configured to be in an off state, and the pulse generator is configured to switch to the second switching state immediately following the first switching state, along with all the other limitations as required by claim 11.
The prior art of record fails to disclose or make obvious a pulse generator comprising, the first constant voltage generator includes: a sampler configured to sample the output voltage in the first switching state, a first calculator configured to generate a difference value by comparing a sampled value of the output voltage and a reference voltage, a PI controller configured to generate a feedback value based on the difference value, and a second calculator configured to generate a first constant voltage by calculating the reference voltage and the feedback value, along with all the other limitations as required by claim 14.
The prior art of record fails to disclose or make obvious a pulse generator comprising: wherein an output voltage is output through the output node, and the output voltage includes signals generated by sequentially switching between a first switching state, a second switching state, and a third switching state, in the first switching state, the first switch and the second switch are configured to be in an on state, and the third switch and the fourth switch are configured to be in an off state, in the second switching state, the first switch is configured to be in an on state, and the second switch, the third switch, and the fourth switch are configured to be in an off state, and in the third switching state, the second switch and the third switch are configured to be in an on state, and the first switch and the fourth switch are configured to be in an off state, along with all the other limitations as required by claim 15.
The prior art of record fails to disclose or make obvious a pulse generator comprising: when the second switch is configured to be in an off state, a current is supplied to the second constant voltage generator and the first constant voltage generator through the second voltage node, a body diode of the fourth switch, a body diode of the third switch, the output node, the first clamping diode, and a body diode of the first switch, along with all the other limitations, along with all the other limitations as required by claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (KR 102657484) discloses a high voltage pulse generator. Moon (KR 20250154753) discloses voltage waveform modulator.
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/PATRICK O NEILL/ Primary Examiner, Art Unit 2836
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