DETAILED ACTION
Election/Restrictions
Claims 11-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/04/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7, and 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al (US 2018/0144867) in view of AKAZAWA et al (US 2012/0188684).
Regarding claim 1, PARK teaches a multilayer electronic component (Fig. 1-10) comprising: a body (Fig. 1, 110) including a dielectric layer (Fig. 2, 111) and first and second internal electrode layers (Fig. 2, 122/121) alternately disposed with the dielectric layer positioned between them in a first direction (Fig. 1, Z), the body further including a first surface and a second surface (Fig. 1, 1 and 2) opposing each other in the first direction (Fig. 1), a third surface and a fourth surface (Fig. 1, 3 and 4) connected to the first and second surfaces and opposing each other in a second direction (Fig. 1, X), and a fifth surface and a sixth surface (Fig. 1, 5 and 6) connected to the first to fourth surfaces and opposing each other in a third direction (Fig. 1, Y), the first internal electrode layer including a first internal electrode exposed to the fifth and sixth surfaces (Fig. 2B), and the second internal electrode layer including a second internal electrode exposed to the third and fourth surfaces (Fig. 2A); a first external electrode and a second external electrode (Fig. 1, 151/152) disposed on the third and fourth surfaces, respectively (Fig. 1), and connected to the second internal electrode (Fig. 1 and 2); a third external electrode and a fourth external electrode (Fig. 1, 153/154) disposed on the fifth and sixth surfaces (Fig. 1), respectively, and connected to the first internal electrode (Fig. 1 and 2); a first insulating portion and a second insulating portion (Fig. 1, 141/142) spaced apart from each other in the second direction with the third external electrode interposed therebetween on the fifth surface (Fig. 1); and a third insulating portion and a fourth insulating portion (Fig. 1, 143/144) spaced apart from each other in the second direction with the fourth external electrode interposed therebetween on the sixth surface (Fig. 1).
However, PARK fails to teach that the first internal electrode layer includes a first internal electrode exposed to the fifth and sixth surfaces, and a first dummy electrode spaced apart from the first internal electrode, and the second internal electrode layer including a second internal electrode exposed to the third and fourth surfaces, and a second dummy electrode spaced apart from the second internal electrode and wherein the first dummy electrode overlaps an exposed portion of the second internal electrode in the first direction, and the second dummy electrode overlaps an exposed portion of the first internal electrode in the first direction.
AKAZAWA teaches that the first internal electrode layer (Fig. 13, 4) includes a first internal electrode exposed to the fifth and sixth surfaces (Fig. 13, top and bottom sides), and a first dummy electrode (Fig. 13, 41) spaced apart from the first internal electrode (Fig. 13), and the second internal electrode layer (Fig. 12, 3) including a second internal electrode (Fig. 12, 3) exposed to the third and fourth surfaces (Fig. 12, left and right sides), and a second dummy electrode (Fig. 12, 42) spaced apart from the second internal electrode (Fig. 12) and wherein the first dummy electrode overlaps an exposed portion of the second internal electrode in the first direction (Fig. 12-13), and the second dummy electrode overlaps an exposed portion of the first internal electrode in the first direction (Fig. 12-13).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of AKAZAWA to the invention of PARK, in order to create a capacitor with an improved electrification efficiency (AKAZAWA [0021]).
Regarding claim 2, PARK, as modified by AKAZAWA, further teaches that the first to fourth insulating portions are each connected to at least a portion of the exposed portion of the first internal electrode (Fig. 4).
Regarding claim 4, PARK, as modified by AKAZAWA, further teaches that regions of the first and second internal electrodes that are exposed through one surface of the body each have a substantially constant size in the second direction and a substantially constant size in the third direction (Fig. 4).
Regarding claim 5, PARK, as modified by AKAZAWA, further teaches that the first internal electrode is exposed on the fifth and sixth surfaces through a plurality of lead portions and is connected to the third and fourth external electrodes as well as the first to fourth insulating portions (Fig. 2-4).
Regarding claim 7, PARK, as modified by AKAZAWA, further teaches that the first internal electrode includes a first main portion (PARK Fig. 2B, 122a), and a first lead portion (PARK Fig. 2B, 122b/122c) extending from the first main portion, the first lead portion includes a 1-1 lead portion (PARK Fig. 2B, 122b) exposed to the fifth surface and at least partially connected to the third external electrode (PARK Fig. 2B, 122b), and a 1-2 lead portion (PARK Fig. 2B, 122c) exposed to the sixth surface and at least partially connected to the fourth external electrode (PARK Fig. 2B, 122c), and the first dummy electrode includes a 1-1 dummy electrode (AKAZAWA Fig. 13, 41 on left) exposed to the third surface, and a 1-2 dummy electrode (AKAZAWA Fig. 13, 41 on right) spaced apart from the 1-1 dummy electrode and exposed to the fourth surface, the second internal electrode includes a second main portion (PARK Fig. 2A, center of 121), and a second lead portion (PARK Fig. 2A, ends of 121) extending from the second main portion, the second lead portion includes a 2-1 lead portion (PARK Fig. 2A, left end of 121) exposed to the third surface and connected to the first external electrode, and a 2-2 lead portion exposed (PARK Fig. 2A, right of 121) to the fourth surface and connected to the second external electrode, and the second dummy electrode includes a 2-1 dummy electrode (AKAZAWA Fig. 12, 42 on bottom) exposed to the fifth surface and a 2-2 dummy electrode (AKAZAWA Fig. 12, 42 on top) exposed to the sixth surface, and the 1-1 dummy electrode overlaps the 2-1 lead portion in the first direction (When combined), the 1-2 dummy electrode overlaps the 2-2 lead portion in the first direction (When combined), the 2-1 dummy electrode overlaps the 1-1 lead portion in the first direction (When combined), and the 2-2 dummy electrode overlaps the 1-2 lead portion in the first direction (When combined).
Regarding claim 13, PARK teaches a multilayer electronic component (Fig. 1-10) comprising: a body (Fig. 1, 110) including a dielectric layer (Fig. 2, 111) and first and second internal electrode layers (Fig. 2, 122/121) alternately disposed with the dielectric layer there-between in a first direction (Fig. 1, Z), and including a first surface and a second surface (Fig. 1, 1 and 2) opposing each other in the first direction (Fig. 1), a third surface and a fourth surface (Fig. 1, 3 and 4) connected to the first and second surfaces and opposing each other in a second direction (Fig. 1, X), and a fifth surface and a sixth surface (Fig. 1, 5 and 6) connected to the first to fourth surfaces and opposing each other in a third direction (Fig. 1, Y), the first internal electrode layer including a first internal electrode exposed to the fifth and sixth surfaces (Fig. 2B), and the second internal electrode layer including a second internal electrode exposed to the third and fourth surfaces (Fig. 2A); a first external electrode and a second external electrode (Fig. 1, 151/152) disposed on the third and fourth surfaces, respectively (Fig. 1), and connected to the second internal electrode (Fig. 1 and 2); a third external electrode and a fourth external electrode (Fig. 1, 153/154) disposed on the fifth and sixth surfaces (Fig. 1), respectively, and connected to the first internal electrode (Fig. 1 and 2); an insulating portion (Fig. 1, 141) disposed on at least one surface of the body (Fig. 1), covering the exposed portions of at least one of the internal electrodes (Fig. 1), and positioned between at least two external electrodes (Fig. 1).
However, PARK fails to teach that the first internal electrode layer includes a first internal electrode exposed to the fifth and sixth surfaces, and a first dummy electrode disposed to be spaced apart from the first internal electrode, and the second internal electrode layer including a second internal electrode exposed to the third and fourth surfaces, and a second dummy electrode disposed to be spaced apart from the second internal electrode and wherein the first dummy electrode overlaps an exposed portion of the second internal electrode in the first direction, and the second dummy electrode overlaps an exposed portion of the first internal electrode in the first direction.
AKAZAWA teaches that the first internal electrode layer (Fig. 13, 4) includes a first internal electrode exposed to the fifth and sixth surfaces (Fig. 13, top and bottom sides), and a first dummy electrode (Fig. 13, 41) disposed to be spaced apart from the first internal electrode (Fig. 13), and the second internal electrode layer (Fig. 12, 3) including a second internal electrode (Fig. 12, 3) exposed to the third and fourth surfaces (Fig. 12, left and right sides), and a second dummy electrode (Fig. 12, 42) disposed to be spaced apart from the second internal electrode (Fig. 12) and wherein the first dummy electrode overlaps an exposed portion of the second internal electrode in the first direction (Fig. 12-13), and the second dummy electrode overlaps an exposed portion of the first internal electrode in the first direction (Fig. 12-13).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of AKAZAWA to the invention of PARK, in order to create a capacitor with an improved electrification efficiency (AKAZAWA [0021]).
Regarding claim 14, PARK, as modified by AKAZAWA, further teaches that the insulating portion is disposed on the fifth and sixth surfaces (Fig. 1, 141 and 143) of the body and is configured to cover at least part of the first internal electrode and the second internal electrode exposed on those surfaces (Fig. 1-3).
Regarding claim 15, PARK, as modified by AKAZAWA, further teaches that the insulating portion comprises first and second insulating portions (Fig. 1, 141/142) disposed to be spaced apart from each other on opposite sides, in the second direction, of the third external electrode (Fig. 1), and third and fourth insulating portions (Fig. 1, 143/144) disposed to be spaced apart from each other on opposite sides, in the second direction, of the fourth external electrode (Fig. 1).
Regarding claim 16, PARK, as modified by AKAZAWA, further teaches that at least one of the first or second insulating portions is connected to the exposed portions of the first internal electrode on the fifth surface (Fig. 4-5), and at least one of the third or fourth insulating portion is connected to the exposed portions of the first internal electrode on the sixth surface (Fig. 4-5).
Regarding claim 17, PARK, as modified by AKAZAWA, further teaches that the insulating portion comprises a plurality of insulating portions spaced apart from each other (Fig. 1, 141-144), some of the plurality of insulating portions are connected to the first internal electrode on the fifth surface (Fig. 1), and others of insulating portions are connected to the first internal electrode on the sixth surface (Fig. 1).
Allowable Subject Matter
Claims 3, 6, and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein the first and second internal electrodes each have a substantially constant size in the second direction and a substantially constant size in the third direction” in combination with the other claim limitations.
Regarding claim 6, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein the second internal electrode is further exposed on the fifth and sixth surfaces through a plurality of lead portions and is connected to the first to fourth insulating portions” in combination with the other claim limitations.
Regarding claims 8-10, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein at least a portion of the 1-1 lead portion is further connected to the first and second insulating portions, and at least a portion of the 1-2 lead portion is further connected to the third and fourth insulating portions” in combination with the other claim limitations.
Additional Relevant Prior Art:
KIM et al (US 2013/0058006) teaches relevant art in Fig. 1-9.
SAKURATANI et al (US 2014/0133063) teaches relevant art in Fig. 1-12.
PARK et al (US 2015/0021082) teaches relevant art in Fig. 1-8.
MASUNARI (US 2017/0256359) teaches relevant art in Fig. 1-16.
SAWADA et al (US 2017/0352479) teaches relevant art in Fig. 1-23.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2847
Prosecution Insights