DETAILED ACTION
This FINAL action is in response to Application No. 18/999,542 originally filed 12/23/2024. The amendment presented on 08/12/2026 which provides amendments to claims 1-6, and 8-9 is hereby acknowledged.
Currently Claim(s) 1-17 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-8, 11, and 13-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. U.S. Patent Application Publication No. 2007/0171176 A1 hereinafter Kwon.
Consider Claim 1:
Kwon discloses a light emitting device comprising: (Kwon, See Abstract.)
a plurality of light emitting elements arranged in a plurality of rows and a plurality of columns; a signal output circuit configured to drive the plurality of light emitting elements; and (Kwon, [0114], “Referring to FIG. 9, the flat panel display device according to the embodiment of the present invention includes: a display region 30 including a plurality of pixels 40 connected to scan lines S[1] to S[n] and data lines D[1] to D[m]; a scan driver 10 for driving the scan lines S[1] to S[n]; a data driver 20 for driving the data lines D[1] to D[m]; and a timing controller 50 for controlling the scan driver 10 and the data driver 20.”)
a voltage generating circuit configured to generate a plurality of reference voltages, (Kwon, [0067], “In the embodiment of FIG. 4, the signals S1, S2, S3, S4 and a signal E are provided from the switching signal generator 330 as shown in FIG. 3, and the high level and the low level of reference voltages are provided from the reference voltage generator 320. Here, the signal E is for controlling the operations of the first, second, third, and fourth switches SW1, SW2, SW3, SW4 and the demultiplexer 316.”)
wherein the signal output circuit includes a plurality of column circuits corresponding to the plurality of columns, each column circuit comprising:
a digital-analog converter is configured to select a reference voltage from among the generated plurality of reference voltages according to image data; (Kwon, [0097], “However, the data driver includes the DAC 300 as described above with reference to FIG. 3 to FIG. 6 and the detailed description of the DAC 300 (including its structures and operations) will not be provided again in more detail”)
a voltage holding circuit configured to hold the selected reference voltage; and (Kwon, [0106], “The holding latch unit 730 receives and stores the data from the sampling latch unit 720 when a source output enable (SOE) signal is input. That is, the holding latch unit inputs and stores the 8 bits of the digital data provided in a parallel state.”)
a driver circuit configured to drive a signal line based on the selected reference voltage held by the voltage holding circuit. (Kwon, [0064], “Therefore, as shown, the gray scale generator 310 according to the embodiment of the present invention further includes a demultiplexer 316 for distinguishing and supplying reference voltage for each data line.”)
Consider Claim 3:
Kwon discloses the light emitting device according to claim 1, wherein the voltage holding circuit holds the voltages corresponding to the plurality of reference voltages in a plurality of capacitor elements. (Kwon, [0043], “For example, instead of using the two neighboring data lines as the sampling capacitor and/or the holding capacitor, the present invention can use the sum values of the parasitic capacitance components existing in two or more data lines as the sampling capacitor and/or the holding capacitor and/or can also use the respective parasitic components existing in the two or more data lines receiving the same colors of data as the sampling capacitor and/or the holding capacitor.”)
Consider Claim 4:
Kwon discloses the light emitting device according to claim 3, wherein the plurality of reference voltages are supplied to the plurality of capacitor elements at different timings. (Kwon, [0055], “To put it another way, the gray scale voltage corresponding to the pixel connected to a first scan line S[1a] is generated and applied in the first line time and the gray scale voltage corresponding to the pixel connected to the second scan line S[1 b] is generated and applied in a second line time so that the sum of the two line times becomes (or can be referred to as) an existing line time. Here, the line time corresponds to the period within one horizontal period 1H.”)
Consider Claim 5:
Kwon discloses the light emitting device according to claim 1, wherein the voltage holding circuit, after being connected with the voltage generating circuit and holding the voltages corresponding to the plurality of reference voltages, disconnects the connection and supplies the held voltage among voltages corresponding to the plurality of reference voltages to the digital-to-analog converter. (Kwon, [0060], “Referring to FIG. 4, the gray scale generator 310 includes: a sampling capacitor C_samp 312 formed by parasitic capacitance components in a first data line 342; a holding capacitor C_hold 314 formed by parasitic capacitance components in a second data line 344; a first switch SW1 for controlling a reference voltage at a high level (or at a high voltage level) VH to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; a second switch SW2 for controlling a reference voltage at a low level (or at a low voltage level) VL to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; and a third switch SW3 provided between the sampling capacitor and the holding capacitor for applying the charge sharing between the sampling capacitor 312 and the holding capacitor 314.”)
Consider Claim 6:
Kwon discloses the light emitting device according to claim 1, wherein the plurality of reference voltages include a plurality of voltage signals. (Kwon, [0044], “Referring to FIG. 3, the DAC 300 according to an embodiment of the present invention includes: a gray scale generator 310 for executing the charge sharing (or sharing of charges) between first data lines 342 and second data lines 344, respectively; a switching signal generator 330 for providing operation control signals for a plurality of switches provided in the gray scale generator 310; and a reference voltage generator 320 for generating reference voltages and providing them to the gray scale generator 310.”)
Consider Claim 7:
Kwon discloses the light emitting device according to claim 1, wherein the voltage holding circuit is shared among at least two column circuits among the plurality of column circuits. (Kwon, [0060], “Referring to FIG. 4, the gray scale generator 310 includes: a sampling capacitor C_samp 312 formed by parasitic capacitance components in a first data line 342; a holding capacitor C_hold 314 formed by parasitic capacitance components in a second data line 344; a first switch SW1 for controlling a reference voltage at a high level (or at a high voltage level) VH to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; a second switch SW2 for controlling a reference voltage at a low level (or at a low voltage level) VL to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; and a third switch SW3 provided between the sampling capacitor and the holding capacitor for applying the charge sharing between the sampling capacitor 312 and the holding capacitor 314.”)
Consider Claim 8:
Kwon discloses the light emitting device according to claim 1, wherein the digital-to-analog converter includes a resistor string configured to divide the plurality of reference voltages. (Kwon, [0017], “As shown in FIG. 2, the DAC 140 uses a reference voltage generator 142 having R-strings R1, R2, . . . Rn for generating correct gray scale voltages and/or gamma-corrections, and includes a ROM type of a switch array 146 for selecting the voltages generated through the reference voltage generator 142.”)
Consider Claim 11:
Kwon discloses an electronic device comprising: a display unit including the light emitting device according to claim 1; a housing in which the display unit is arranged; and a communication unit provided in the housing and configured to communicate with an external unit. (Kwon, [0005], “A flat panel display device generally includes a display panel, a scan driver, and a data driver. The scan driver sequentially outputs scan driving signals to a plurality of scan lines formed on the display panel, and the data driver outputs R, G, B image signals to data lines on the display panel. Non-limiting examples of a flat panel display device include a liquid crystal display device, a field emission display device, a plasma display panel, a light emitting display device, etc.”)
Consider Claim 13:
Kwon discloses a moving body comprising: a lamp including the light emitting device according to claim 1; and a body in which the lamp is provided. (Kwon, [0005], “A flat panel display device generally includes a display panel, a scan driver, and a data driver. The scan driver sequentially outputs scan driving signals to a plurality of scan lines formed on the display panel, and the data driver outputs R, G, B image signals to data lines on the display panel. Non-limiting examples of a flat panel display device include a liquid crystal display device, a field emission display device, a plasma display panel, a light emitting display device, etc.”)
Consider Claim 14:
Kwon discloses the light emitting device according to claim 1, wherein the voltage holding circuit comprising a capacitor and a switch connected between the capacitor and the voltage generating circuit. (Kwon, [0060], “Referring to FIG. 4, the gray scale generator 310 includes: a sampling capacitor C_samp 312 formed by parasitic capacitance components in a first data line 342; a holding capacitor C_hold 314 formed by parasitic capacitance components in a second data line 344; a first switch SW1 for controlling a reference voltage at a high level (or at a high voltage level) VH to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; a second switch SW2 for controlling a reference voltage at a low level (or at a low voltage level) VL to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; and a third switch SW3 provided between the sampling capacitor and the holding capacitor for applying the charge sharing between the sampling capacitor 312 and the holding capacitor 314.”)
Consider Claim 15:
Kwon discloses the light emitting device according to claim 1, wherein the voltage holding circuit comprising a plurality of holding capacitors, each of the plurality of holding capacitors holes corresponding voltage among the voltages held in the voltage holding circuit. (Kwon, [0060], “Referring to FIG. 4, the gray scale generator 310 includes: a sampling capacitor C_samp 312 formed by parasitic capacitance components in a first data line 342; a holding capacitor C_hold 314 formed by parasitic capacitance components in a second data line 344; a first switch SW1 for controlling a reference voltage at a high level (or at a high voltage level) VH to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; a second switch SW2 for controlling a reference voltage at a low level (or at a low voltage level) VL to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; and a third switch SW3 provided between the sampling capacitor and the holding capacitor for applying the charge sharing between the sampling capacitor 312 and the holding capacitor 314.”)
Consider Claim 16:
Kwon discloses the light emitting device according to claim 15, wherein the voltage input to the digital-analog converter is a voltage held in a holding capacitor among the plurality of holding capacitor, and wherein the voltage corresponds to the digital signal input to the digital-analog converter. (Kwon, [0060], “Referring to FIG. 4, the gray scale generator 310 includes: a sampling capacitor C_samp 312 formed by parasitic capacitance components in a first data line 342; a holding capacitor C_hold 314 formed by parasitic capacitance components in a second data line 344; a first switch SW1 for controlling a reference voltage at a high level (or at a high voltage level) VH to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; a second switch SW2 for controlling a reference voltage at a low level (or at a low voltage level) VL to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; and a third switch SW3 provided between the sampling capacitor and the holding capacitor for applying the charge sharing between the sampling capacitor 312 and the holding capacitor 314.”)
Consider Claim 17:
Kwon discloses the light emitting device according to claim 1, wherein the voltage holding circuit comprising a plurality of sets of a holding capacitor and a switch, in each sets, the switch is connected between the holding capacitor and the voltage generating circuit. (Kwon, [0060], “Referring to FIG. 4, the gray scale generator 310 includes: a sampling capacitor C_samp 312 formed by parasitic capacitance components in a first data line 342; a holding capacitor C_hold 314 formed by parasitic capacitance components in a second data line 344; a first switch SW1 for controlling a reference voltage at a high level (or at a high voltage level) VH to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; a second switch SW2 for controlling a reference voltage at a low level (or at a low voltage level) VL to be supplied to the sampling capacitor 312 depending on the respective bit values of the input digital data; and a third switch SW3 provided between the sampling capacitor and the holding capacitor for applying the charge sharing between the sampling capacitor 312 and the holding capacitor 314.”)
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. U.S. Patent Application Publication No. 2007/0171176 A1 as applied to claim 1 above, and further in view of Kim et al. U.S. Patent Application Publication No. 2017/0309217 A1 hereinafter Kim.
Consider Claim 2:
Kwon discloses the light emitting device according to claim 1, however does not suggest further comprising: a pre-charge circuit configured to pre-charge output of the digital-to-analog converter to a predetermined voltage before the held voltage among the voltages corresponding to the plurality of reference voltages is supplied to the digital-to-analog converter.
Kim however teaches that it was a known technique to those of ordinary skill in the art to provide a pre-charge circuit configured to pre-charge output of the digital-to-analog converter to a predetermined voltage before the held voltage among the voltages corresponding to the plurality of reference voltages is supplied to the digital-to-analog converter. (Kim, [0042-0056], [0011], “In an embodiment, a display device may include: a voltage generator configured to generate precharge voltages; source driving channels each including a digital-analog converter configured to convert image data into a source driving signal and an output buffer configured to output the source driving signal to a data output line; a precharge unit configured to precharge the data output line by selecting one of the precharge voltages; and a precharge controller configured to decide whether to perform a precharge operation on each of the source driving channels depending on a variation of the image data, and control the precharge unit to select one of the precharge voltages when the performance of the precharge operation is decided.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to pre-charge output of the digital-to-analog converter as this was a known technique in view of Kim and would have been utilized for art recognized purpose of thereby reducing power consumption and heat generation. (Kim, [0052])
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. U.S. Patent Application Publication No. 2007/0171176 A1 as applied to claim 1 above, and further in view of Wang et al. U.S. Patent Application Publication No. 2004/0125422 A1 hereinafter Wang.
Consider Claim 9:
Kwon discloses the light emitting device according to claim 1, however does not appear to suggest wherein the voltage holding circuit supplies the held voltage among the voltages corresponding to the plurality of reference voltages to the digital-to-analog converter via a buffer circuit.
Wang however teaches it was a known technique in the art to provide wherein the voltage holding circuit supplies the held voltage among the voltages corresponding to the plurality of reference voltages to the digital-to-analog converter via a buffer circuit. (Wang, [0018-0021], [0019], “The gamma reference voltages for the three primary colors are output during corresponding time slots R:ON, G:ON and B:ON. The digital-to-analog converters 3a, 3b and 3c receive the image data of and the gamma reference voltages for the three primary colors respectively from the sample and hold register 2 and the gamma multiplexer 4, and output calibrated image signals of the three primary colors, respectively. The unit gain buffers 5a, 5b and 5c respectively receive the calibrated image signals of the three primary colors from the digital-to-analog converters 3a, 3b and 3c through the switches Rsw, Gsw and Bsw in the predetermined sequence of the primary colors. The switches Rsw, Gsw and Bsw are closed during the corresponding time slots R:ON, G:ON and B:ON, whereby the sub-pixel data is output to the pixel array through the R, G and B data lines.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a buffer inline as this was a known technique in view of Wang and would have been utilized for the purpose of to provide a data driver applying gamma correction with different gamma reference voltages to image data of the three primary colors, whereby an optimally calibrated color image with adjustable color temperature can be generated. (Wang, [0006])
Claim Rejections - 35 USC § 103
Claim(s) 10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. U.S. Patent Application Publication No. 2007/0171176 A1 as applied to claim 1 above, and further in view of Akiyama et al. U.S. Patent Application Publication No. 2022/0172679 A1 hereinafter Akiyama.
Consider Claim 10:
Kwon teaches wherein the display unit includes the light emitting device according to claim 1. (Kwon, See Claim 1 above)
Kwon however does not appear to suggest a photoelectric conversion device comprising: an optical unit including a plurality of lenses; an image capturing element configured to receive light that has passed through the optical unit; and a display unit configured to display an image captured by the image capturing element.
Akiyama however teaches that it was a known to those of skill in the art before the effective filing date of the invention that a light emitting device would be implemented in a photoelectric conversion device comprising: an optical unit including a plurality of lenses; an image capturing element configured to receive light that has passed through the optical unit; and a display unit configured to display an image captured by the image capturing element. (Akiyama, [0110-0112], [0112] “The imaging apparatus 1100 includes a not-illustrated optical unit. The optical unit includes a plurality of lenses and forms an image on an image sensor accommodated in the housing 1104. Focus can be adjusted by adjusting relative positions of the plurality of lenses. Such an operation can also be performed automatically. The imaging apparatus 1100 may be referred to as a photoelectric conversion apparatus. The photoelectric conversion apparatus may use an imaging method such as a method for detecting differences from previous images and a method for cutting out images from a constantly recorded image, instead of successively capturing images.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide the light emitting device according to claim 1 as recognized as part of the ordinary capabilities of one skilled in the art in view Akiyama. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product e.g. device of claim 1) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Consider Claim 12:
Kwon discloses a lighting device comprising: a light source including the light emitting device according to claim 1; (Kwon, See Claim 1 above.)
Kwon however does not suggest or provide details of a light diffusion unit or an optical film configured to transmit light emitted by the light source.
Akiyama however teaches that it was a known to those of skill in the art before the effective filing date of the invention that a light emitting device would be implemented in a light diffusion unit or an optical film configured to transmit light emitted by the light source. (Akiyama, [0118-0122], [0118], “FIG. 17A is a schematic diagram illustrating an example of an illumination apparatus according to the present exemplary embodiment. An illumination apparatus 1400 may include a housing 1401, a light source 1402, a circuit substrate 1403, an optical film 1404, and a light diffusion unit 1405. The light source 1402 may include any of the foregoing light emitting apparatuses 101, 601, and 111. The optical film 1404 may be a filter for improving the color rendering property of the light source 1402. The light diffusion unit 1405 can effectively diffuse the light from the light source 1402 and deliver the light to a wide range. An example of the light diffusion unit 1405 is a light diffusion film LIGHT-UP manufactured by KIMOTO Co., Ltd. The optical film 1404 and the light diffusion unit 1405 may be located on the light emission side of the illumination apparatus 1400.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide the light emitting device according to claim 1 as recognized as part of the ordinary capabilities of one skilled in the art in view Akiyama. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product e.g. device of claim 1) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Granting of After Final Interviews: “Interviews merely to restate arguments of record or to discuss new limitations which would require more than nominal reconsideration or new search should be denied.” See MPEP § 713.09.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached on 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michael J Jansen II/ Primary Examiner, Art Unit 2626
Prosecution Insights