DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of claims 8-18, corresponding to Invention II and Species 2 in the reply filed on May 26, 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (lDS) submitted on December 23, 2024 and May 26, 2026 are in compliance with the provisions of 37 CFR 1.97 and have been considered by the Examiner.
The information disclosure statement filed December 23, 2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein that lacks a legible copy has not been considered. Specifically, cited foreign patent documents C48, C58, C62, C70, C75, and C96 have not been submitted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Berkovich et al. (US Pub. 2021/0368124; hereinafter referred to as Berkovich ‘124), in view of Berkovich et al. (US Pub. 2021/0044742; hereinafter referred to as Berkovich ‘742).
In regard to claim 8, note Berkovich ‘124 discloses a pulse-width modulation (PWM) image sensor comprising a charge-to-time converter (CTC) circuit, the CTC circuit comprising a photodiode (paragraphs 0100-0101, and figures 6A & 6C: 602), a reset gate (paragraphs 0100-0101, and figure 6A & 6C: 605), and a comparator (paragraphs 0100-0101, and figure 6A & 6C: 607), and a time-to-digital converter (TDC) circuit (paragraphs 0100-0101, and figure 6C: 616), wherein a reset signal is applied to the reset gate to initiate a detection period, during the detection period, the photodiode accumulates a number of electrons, and when the number of electrons reaches a threshold number of electrons, the CTC circuit transmits a write signal, from the comparator, to the TDC circuit (paragraphs 0100-0102, and figure 6D; when the signal reaches the threshold, the latch signal is sent to the TDC circuit 616).
Therefore, it can be seen that the primary reference fails to explicitly disclose a top wafer and a bottom wafer, wherein the top wafer comprises the CTC circuit and the bottom wafer comprises the TDC circuit.
In analogous art, Berkovich ‘742 discloses an image sensor comprising a top wafer and a bottom wafer (figure 10), and that various pixel components are distributed across the top and bottom wafers (paragraphs 0134-0137). Berkovich ‘742 teaches that the use of a top wafer and a bottom wafer, with various pixel components being distributed across the top and bottom wafers is preferred in order to increase data transmission speeds and decrease power requirements (paragraph 0135). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the primary reference to include a top wafer and a bottom wafer, wherein the top wafer comprises the CTC circuit and the bottom wafer comprises the TDC circuit, in order to increase data transmission speeds and decrease power requirements, as suggested by Berkovich.
In regard to claim 9, note Berkovich ‘124 discloses that the TDC circuit is a static random-access memory comprising a number of latches, and the write signal latches a count in the number of latches (paragraphs 0101, 0146, and figures 6C, 9C & 10C: 616).
In regard to claim 10, note Berkovich ‘124 discloses a threshold voltage is applied to the comparator, and the threshold number of electrons corresponds to the threshold voltage applied to the comparator (paragraphs 0100-0102, and figure 6C-6D: Vref; when the signal level matches the threshold Vref, the latch signal is generated by the comparator).
In regard to claim 11, note Berkovich ‘124 discloses the CTC circuit and the TDC circuit comprise a pixel, and the PWM image sensor further comprises a number of pixels, each pixel of the number of pixels comprising a respective CTC circuit and a respective TDC circuit pair (paragraphs 0100-0104, and figures 6A & 6C: 600, 602, 605, 607, 616; each pixel in the array 600 includes the CTC comprising photodiode 602, reset gate 605, and comparator 607, as well as TDC 616).
In regard to claim 12, note Berkovich ‘124 discloses that each pixel of the number of pixels are arranged in an array and are read row-by-row (paragraphs 0116-0118, and figure 6A: 600, and figure 8A: 806; the pixel array is read out by row control circuit 806).
In regard to claim 13, note Berkovich ‘742 discloses that the top wafer and the bottom wafer are communicatively coupled by at least one of a vertical transfer gate, a through-silicon via, or a bond pad (paragraphs 0136-0137, and figure 10B).
Allowable Subject Matter
Claims 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISS S YODER III whose telephone number is (571)272-7323. The examiner can normally be reached M-F 9:00-5:00 PM.
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/CHRISS S YODER III/Examiner, Art Unit 2638