Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 10- 2021-0008793, filed on January 21, 2021.
Information Disclosure Statement
As required by M.P.E.P. 609 (C), the applicant’s submission of the information Disclosure Statement dated 12/23/2024 & 08/11/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over YUN et al. (Pub. No.: US 2018/0151218) in view of Ochiai (Patent No.: US 8,516,214).
Regarding independent claim 17, YUN discloses a memory controller (Fig.2: memory controller 20) for controlling a plurality of memory devices, the memory controller (Fig.2: memory controller 20 ) comprising:
at least one data signal pin connected to a data signal line (Fig.2: shared channel 50) in a single channel connected between the memory controller (Fig.2: memory controller 20) and the plurality of memory devices (Fig.2: first memory device 100a and a second memory device 100b) (Fig.2 and [0038]-[0048]: a memory controller connected to a plurality of memory devices via a single channel);
a data extraction circuit that receives, through the at least one data signal pin, a first output data output from a first memory device (Fig.2: first memory device 100a) among the plurality of memory devices (Fig.2: first memory device 100a and a second memory device 100b) and obtains internal data corresponding to the first output data of the first memory device (Fig.2: first memory device 100a (Fig.2, [0039] and [0064]): data output from memory devices is received by the memory controller through a data interface and processed internally);
a command logic circuit that generates a command to be provided to a second memory device (Fig.2: a second memory device 100b) among the plurality of memory devices (Fig.2: first memory device 100a and a second memory device 100b) and outputs control signals based on the command (Fig.2, [0047]-[0049] and [0107]: the memory controller generates commands (e.g., refresh commands REF1, REF2) and controls memory device operations); and
a switch circuit that transmits the command for the second memory device (Fig.2: a second memory device 100b) to the second memory device (Fig.2: a second memory device 100b) through the at least one data signal pin and the data signal line in response to the control signals (Fig.2, [0038]-[0041] and [00069]: commands are transmitted from the memory controller to memory devices through the shared channel],
wherein the first output data and the command are loaded on the data signal line at the same time (Fig.2, [0038]-[0041] and [0069]: the same channel is used to transmit both command signals and data between the memory controller and the plurality of memory devices and thus, it is reasonably interpreted that both command and data are present on the data signal line during operation of the system).
However, YUN does not specifically teach wherein the first output data of the first memory device and the command for the second memory device are transmitted in both directions of the data signal line in the single channel.
Ochiai teaches wherein the first output data of the first memory device and the command for the second memory device are transmitted in both directions of the data signal line in the single channel (Fig. and col.2, lines 22-27: 160 is a data issuing control circuit, and drives the data signal 106 after a time period equivalent to the write latency held in the latency information holding circuit 140 has elapsed since the command issuing control circuit 150 issued a command. 170 is a data reception control circuit, and receives data read from the memory devices 191 and 192.) (see also claim 16: multiple memories are controlled by a single memory controller through a common data signal line. Consequently, the memory controller receives the first data through the same data signal line through which it sent a command to the second memory).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the common data signal line, as taught by Ochiai into the memory controller that controls overall operations of the memory system and is electrically connected to the channel of YUN, in order to help reduce signal interference and noise by sharing common data signal line.
Regarding claim 18, YUN teaches wherein the first output data of the first memory device is transmitted to the memory controller at a transmission rate of a first frequency (Fig.2, [0038]-[0041] and [0064]: data is transmitted between memory devices and the memory controller via a shared channel during operation of the memory system), and the command for the second memory device is transmitted to the second memory device at a transmission rate of a second frequency (Fig.2, [0047]-[0049] and [0107]: the memory controller generates commands (e.g., refresh commands REF1, REF2) and controls memory device operations), wherein the first frequency is higher than the second frequency (Fig.2, [0034], [0047]-[0051] and [0088]-[0090]: memory devices perform different numbers of refresh operations (e.g., N and M refresh operations) within refresh periods of substantially the same duration based on commands from the memory controller, which inherently corresponds to different effective transmission rates (frequencies) for data and command operations).
Allowable Subject Matter
Claims 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 19 identifies the distinct features “an on-die termination circuit that provides a termination resistance to the data signal line through the at least one data signal pin, wherein the on-die termination circuit includes: a pull-down resistor connected to a ground voltage line, wherein the pull-down resistor is connected to the at least one data signal pin by a first switch of the switch circuit, wherein the first switch is responsive to a first control signal among the control signals, and when a signal bit of the command for the second memory device is logic low, the data signal line is in a state of a low voltage level through the pull-down resistor and the first switch; and a pull-up resistor connected to a power voltage line, wherein the pull-up resistor is connected to the at least one data signal pin by a second switch of the switch circuit, wherein the second switch is responsive to a second control signal among the control signals, and when the signal bit of the command for the second memory device is logic high, the data signal line is in a state of a high voltage level through the pull-up resistor and the second switch, wherein the high voltage level is higher than a second reference voltage level that is between a power voltage level and a ground voltage level, and the low voltage level is lower than the second reference voltage level", which are not taught or suggested by the prior art of records.
Claim 20, which respectively depends on objected-to claims 19, is allowable for at least the same reasons as claim 19.
Claims 19 and 20 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Reasons of Allowance
Claims 1-16 are allowed.
The closest prior art, YUN et al. (Pub. No.: US 2018/015218), discloses “wherein a first memory device among the plurality of memory devices transmits a first output data output in response to a first read command of the memory controller to the memory controller through the at least one data signal line, the memory controller transmits a second read command for a second memory device among the plurality of memory devices to the second memory device through the at least one data signal line”.
However, the prior art differs from the present invention because the prior art fails to disclose “wherein the first output data and the second command are loaded on the at least one data signal line at the same time, the memory controller changes a voltage level of the at least one data signal line based on the second read command for the second memory device and the first output data of the first memory device is loaded on the at least one data signal line having the changed voltage level, and the first output data of the first memory device and the second read command for the second memory device are transmitted in both directions of the at least one data signal line of the single channel”.
The following is an examiner’s statement of reasons for allowance:
Independent Claim 1 identifies the distinct features “wherein the first output data and the second command are loaded on the at least one data signal line at the same time, the memory controller changes a voltage level of the at least one data signal line based on the second read command for the second memory device and the first output data of the first memory device is loaded on the at least one data signal line having the changed voltage level, and the first output data of the first memory device and the second read command for the second memory device are transmitted in both directions of the at least one data signal line of the single channel", which are not taught or suggested by the prior art of records.
Independent Claim 9 identifies the distinct features “the memory controller transmits write data for a second memory device among the plurality of memory devices to the second memory device through the at least one data signal line, wherein the first output data and the write data are loaded on the data signal line at the same time, a voltage level of the at least one data signal line is changed based on the write data for the second memory device and the first output data of the first memory device is loaded on the at least one data signal line having the changed voltage level, and the first output data of the first memory device and the write data for the second memory device are transmitted in first and second directions of the at least one data signal line of the single channel", which are not taught or suggested by the prior art of records.
Claims 1-16 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records. The above features in conjunction with all other limitations of the dependent and independent claims 1-16 are hereby allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nishikido (Patent No.: US 6,732,217) “Control And Supervisory Signal Transmission System”
Considered for teachings related to a control and supervisory signal transmission system, and in particular, to a control and supervisory signal transmission system wherein a parallel control signal from a controller is converted into a serial signal to transmit it to a remote device, serial-parallel conversion is performed in a controlled section of the remote device to drive the device, a parallel supervisory signal in a sensor section to detect the status of the device is converted into a serial signal to transmit it to the controller, serial-parallel conversion is performed on the serial signal to provide it to the controller, the control signal is superimposed on a clock signal, and the supervisory signal is superimposed on these signals.
Does not disclose or suggest wherein the first output data and the second command are loaded on the at least one data signal line at the same time, the memory controller changes a voltage level of the at least one data signal line based on the second read command for the second memory device and the first output data of the first memory device is loaded on the at least one data signal line having the changed voltage level, and the first output data of the first memory device and the second read command for the second memory device are transmitted in both directions of the at least one data signal line of the single channel.
UETA (Pub. No.: US 2011/0246760) “ELECTRONIC DEVICE AND ELECTRONIC DEVICE SYSTEM”
Considered for teachings related to an electronic device using, for example, a flash memory, and to an electronic device system in which the electronic device is embedded.
Does not disclose or suggest wherein the first output data and the second command are loaded on the at least one data signal line at the same time, the memory controller changes a voltage level of the at least one data signal line based on the second read command for the second memory device and the first output data of the first memory device is loaded on the at least one data signal line having the changed voltage level, and the first output data of the first memory device and the second read command for the second memory device are transmitted in both directions of the at least one data signal line of the single channel.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 10:00 am to 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
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