DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 13-14, 16-18 and 20-24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nojima et al. (USP 11,451,227).
Regarding claim 1, Nojima et al.’s figure 4 shows An apparatus comprising: a current source (Q2, when it is on it acts as a current source) having a current control input (gate control input terminal) and a current source output (source/drain of the transistor Q2), the current source output coupled to a first transistor control terminal (control terminal of Q1); a transistor (Q3) coupled between the first transistor control terminal and a current drain terminal (source/drain of the transistor Q3), the transistor having a second transistor control terminal (control gate terminal of Q3); and an amplifier (214) having a first input, a second input, and an amplifier output, the first input coupled to the first transistor control terminal, the second input coupled to a reference terminal (212), and the amplifier output coupled to the current control input and the second transistor control terminal as called for in claim 1.
Regarding claim 2, the current source (Q2) is configured to provide a current to the first transistor control terminal responsive to a control signal at the amplifier output; and the transistor is configured, responsive to the control signal, to drain away at least some of the current from the first transistor control terminal.
Regarding claim 3, the amplifier is configured to set a state of the control signal based on whether a voltage on the first transistor control terminal exceeds a threshold voltage at the reference terminal (performed by the amplifier 214).
Regarding claim 13, Nojima et al.’s figure 4 shows An apparatus comprising: a current source (Q2 acts as current source when it is turned on) having a current source control input and a current source output, the current source output coupled to a transistor control terminal (gate terminal of Q1); a current sink (Q3) having a current sink control input and coupled between the transistor control terminal and a current drain terminal; and an amplifier (214) having a first input, a second input, and an amplifier output, the first input coupled to the current source output, the second input coupled to a reference terminal, and the amplifier output coupled to the current source control input and the current sink control input as called for in claim 13.
Regarding claim 14, wherein the current sink includes a transistor (Q2) coupled between the current source output and the current drain terminal, the transistor having a second transistor control input coupled to the current sink control input.
Regarding claim 16, wherein the transistor control terminal is of a first transistor which is a high electron mobility transistor (HEMT) (claim 3).
Regarding claim 17, he transistor control terminal of the HEMT includes a p-type gallium nitride (GaN) layer (claim 8).
Regarding claim 18, Nojima et al.’s figure 4 shows a current source (Q2) and a current sink (Q3) coupled to a transistor control terminal; and an amplifier (214) configured to control the current source and the current sink by sensing a voltage at the transistor control terminal as called for in claim 18.
Regarding claim 20, wherein the current sink includes a transistor (Q3) coupled between the transistor control terminal and a current drain terminal.
Regarding claim 21, wherein the transistor control terminal is of a first transistor which is a high electron mobility transistor (HEMT) (claim 3).
Regarding claim 22, wherein the transistor control terminal of the HEMT includes a p-type gallium nitride (GaN) layer (claim 8).
Regarding claim 23, Nojima et al.’s figure 4 shows a circuit comprising A method injecting a first current (Q2 is on) to a control terminal of a transistor; responsive to a voltage of the control terminal exceeding a threshold (performed by the comparator 214), reducing the first current, and sinking a second current (Q3 ) from the control terminal; and responsive to the voltage being at the threshold, maintaining the first current at a non-zero value as called for in claim 23.
Regarding claim 24, responsive to the voltage being below the threshold, disabling the second current (Q3 off).
Claim(s) 1-24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Heckroth et al. (USP 12,155,332).
Regarding claim 1, Heckroth et al.’s figure 6 shows An apparatus comprising: a current source (21) having a current control input (inputs receiving control signal Soff_P0-Soff_pn; Son_P0 to Son_pn) and a current source output (source/drain of the transistors (Mp0-Mpn; Mnpco0-Mnpcn), the current source output coupled to a first transistor control terminal (Vo); a transistor (MNcn0-MNcnn; MNo-Mnn) coupled between the first transistor control terminal and a current drain terminal (source/drain of the transistors MNcn0-MNcnn; MNo-Mnn), the transistor having a second transistor control terminal (control gate terminal of transistors MNcn0-MNcnn; MNo-Mnn); and an amplifier (406, 404) having a first input, a second input, and an amplifier output, the first input coupled to the first transistor control terminal, the second input coupled to a reference terminal (VREF), and the amplifier output coupled to the current control input and the second transistor control terminal as called for in claim 1.
Regarding claim 2, the current source (21) is configured to provide a current to the first transistor control terminal responsive to a control signal at the amplifier output; and the transistor is configured, responsive to the control signal, to drain away at least some of the current from the first transistor control terminal.
Regarding claim 3, the amplifier is configured to set a state of the control signal based on whether a voltage on the first transistor control terminal exceeds a threshold voltage at the reference terminal (performed by the amplifier 406).
Regarding claim 4, wherein the amplifier is configured to: responsive to the voltage being below the threshold voltage, cause the current source to set the current to a first value; and responsive to the voltage being at or above the threshold voltage, cause the current source to set the current to a second value, the second value being non-zero and smaller than the first value (performed by 421 when various switches are turned on and off).
Regarding claim 5, wherein the amplifier is configured to: responsive to the voltage being below the threshold voltage, which disables the transistor (MNcn0-MNcnn; MNo-Mnn); and responsive to the voltage being at or above the threshold voltage, which enables the transistor (MNcn0-MNcnn; MNo-Mnn).
Regarding claim 6, the transistor (MNcn0-MNcnn; MNo-Mnn) is enabled before the current source sets the current to the second value, and is disabled after the current source sets the current to the second value (performed by soft turned off).
Regarding claim 7, further comprising a trimmable current reference coupled to the current source (performed by the switching networks Soff_P0-Soff_pn; Son_P0 to Son_pn).
Regarding claim 8, wherein the first transistor control terminal is of a first transistor which is a high electron mobility transistor (HEMT) (108 is high power driving transistor).
Regarding claim 9, the first transistor control terminal of the HEMT includes a p-type gallium nitride (GaN) layer (108 is capable of having GaN layer since it is a high power driving transistor).
Regarding claim 10, wherein the first transistor (108) is coupled between a switch terminal and a ground terminal, the current source (Soff_P0-Soff_pn; Son_P0 to Son_pn) is coupled to a power supply terminal (VDD), and the current drain terminal is coupled to the ground terminal.
Regarding claim 11, wherein the first transistor (108) is coupled between a power terminal and a switching terminal, the current source is coupled to a bootstrap supply terminal (VDD), and the current drain terminal is coupled to the switching terminal.
Regarding claim 12, the switching terminal is coupled to a load (I load).
Regarding claim 13, Heckroth et al.’s figure 6 shows An apparatus comprising: a current source (Mp0-Mpn; Mnpco0-Mnpcn) having a current source control input and a current source output, the current source output coupled to a transistor control terminal (gate terminal of 108); a current sink (MNcn0-MNcnn; MNo-Mnn) having a current sink control input and coupled between the transistor control terminal and a current drain terminal; and an amplifier (406, 404) having a first input, a second input, and an amplifier output, the first input coupled to the current source output, the second input coupled to a reference terminal (VREF), and the amplifier output coupled to the current source control input and the current sink control input as called for in claim 13.
Regarding claim 14, wherein the current sink includes a transistor (MNcn0-MNcnn; MNo-Mnn) coupled between the current source output and the current drain terminal, the transistor having a second transistor control input coupled to the current sink control input.
Regarding claim 15, further comprising a trimmable current reference coupled to the current source (performed by the switching networks Soff_P0-Soff_pn; Son_P0 to Son_pn).
Regarding claim 16, wherein the transistor control terminal is of a first transistor which is a high electron mobility transistor (HEMT) (108 high power transistor).
Regarding claim 17, the transistor control terminal of the HEMT includes a p-type gallium nitride (GaN) layer (108 is high power transistor which is capable of having GaN layer).
Regarding claim 18, Heckroth et al.’s figure 6 shows a current source (Mp0-Mpn; Mnpco0-Mnpcn) and a current sink (MNcn0-MNcnn; MNo-Mnn) coupled to a transistor control terminal (108); and an amplifier (406, 404) configured to control the current source and the current sink by sensing a voltage at the transistor control terminal as called for in claim 18.
Regarding claim 19, further comprising a trimmable current reference coupled to the current source (performed by the switching networks Soff_P0-Soff_pn; Son_P0 to Son_pn).
Regarding claim 20, wherein the current sink includes a transistor (MNcn0-MNcnn; MNo-Mnn) coupled between the transistor control terminal and a current drain terminal.
Regarding claim 21, wherein the transistor control terminal is of a first transistor which is a high electron mobility transistor (HEMT) (transistor 108 is a high power transistor).
Regarding claim 22, wherein the transistor control terminal of the HEMT includes a p-type gallium nitride (GaN) layer (108 is high power transistor which is capable of having GaN layer).
Regarding claim 23, Heckroth et al.’s figure 6 shows a circuit comprising A method injecting a first current (Mp0-Mpn; Mnpco0-Mnpcn) to a control terminal of a transistor (108); responsive to a voltage of the control terminal exceeding a threshold (performed by the comparator 406), reducing the first current, and sinking a second current (MNcn0-MNcnn; MNo-Mnn) from the control terminal; and responsive to the voltage being at the threshold, maintaining the first current at a non-zero value (Mp0-Mpn; Mnpco0-Mnpcn; one of those transistors remains on) as called for in claim 23.
Regarding claim 24, responsive to the voltage being below the threshold, disabling the second current (MNcn0-MNcnn; MNo-Mnn) .
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2836 5/15/2026
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