DETAILED ACTION
This action responds to Application No. 19/000081, filed 12/23/2024.
Claims 1-14 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/03/2025 and 12/23/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, as follows:
Claims 1 and 13-14, language “dividing a cache space into an N*N cache array” (e.g. claim 1, line 2). This limitation is indefinite, as Applicant has not disclosed what the respective “N” dimensions refer to. They could, for instance, refer to an array of multiple caches, arranged in an N*N grid (for example, 4 caches arranged into 2 rows and 2 columns), or it could refer to the structure of entries within a cache, such as rows in one dimension, and columns/ways in another dimension. As Applicant is unable to determine the intended meaning of this limitation, it is indefinite;
Claim 6, language “in the cache block for storing the message, writing an addresses of other cache blocks except a first cache block into the first cache block, wherein the first cache block is a target cache block selected from the first candidate cache row, and an address of the cache block is configured to indicate a storage location of the message” (lines 4-5). This is non-idiomatic English. It is unclear whether the first cache block is the cache block, and is further unclear which other cache blocks have their addresses written. Furthermore, it is unclear how the address of the cache block indicates the storage location of the message (which is the cache block) if the first cache block is the cache block, and does not include an address of the first cache block;
Claims 7-10 and 12:
Language “the single-port RAM” (e.g. claim 7, lines 1-2). There is insufficient antecedent basis for this limitation in the claim;
Language “the cache block is the single-port RAM” (e.g. claim 7, lines 1-2). It is not clear what it means for the cache block to be the single-port RAM; it appears that the “block” is either a logical or physical data structure within the cache space corresponding to a number of addresses (claim 1, lines 2-5);
Language “before the selecting the cache block for storing […] determining whether a dequeued message exists in the cache array; in response to that the dequeued message exists in the cache array, removing a cache block where the dequeued message is located from the cache array; and […] selecting the cache block for storing the message from the cache array after the cache block is removed” (e.g. claim 7, lines 2-12). This limitation is indefinite, as the timing of selecting the cache block explicitly depends on a condition (determining whether a dequeued message exists) which may or may not occur. In other words, it is unclear how the selecting the cache block can occur after the cache block is removed, if there is no dequeued message that exists in the cache array, and thus no cache block is removed. Furthermore, it is noted that this limitation is subject to interpretation under 35 MPEP § 2111.04(II); accordingly, the existence of a dequeued message is optional, and thus everything that is contingent upon said dequeued message existing is also optional. Finally, it is noted that the limitation “in response to that the dequeued message exists” appears to be missing the word “determining”, and should presumably read “in response to determining that the dequeued message exists”;
Claim 11:
Language “the cache block is the single-port RAM” (lines 1-2). It is not clear what it means for the cache block to be the single-port RAM; it appears that the “block” is either a logical or physical data structure within the cache space corresponding to a number of addresses (claim 1, lines 2-5). The claim depends on claim 5, which discloses that the type of the cache block is a single-port RAM, not that the cache block itself is a single-port RAM;
Language “before the selecting the cache block for storing […] determining whether a dequeued message exists in the cache array; in response to that the dequeued message exists in the cache array, removing a cache block where the dequeued message is located from the cache array; and […] selecting the cache block for storing the message from the cache array after the cache block is removed” (lines 2-12). See claims 7-10 and 12 above.
Claims 2-12 are rejected as being dependent on claim 1 above.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ogawa et al (US 2015/0324294 A1).
Re claim 1, Ogawa discloses the following:
A method for caching a message, comprising (Fig. 9, steps S104 and S107). It is noted that “for caching a message” is intended use, and is not given patentable weight. Nevertheless, Ogawa discloses caching data of a write request (a message) in the cache flash storage (cache);
dividing a cache space into an N*N cache array, wherein N is a natural number greater than zero (Fig. 3, flash memory chips 204). The term “N*N cache array” is indefinite, as noted above. Accordingly, Examiner interprets it as being either 1) a number of rows and columns or ways in a cache, or 2) a number of cache devices arranged into an array. Furthermore, it is noted that N need only be a “natural number greater than zero”, which would include a 1x1 array (i.e. an array comprising a single cache). Ogawa discloses a cache which is divided into a 2x2 array of flash memory chips (Fig. 3, flash memory chips 204);
and each cache block in the cache array has a same size (Fig. 8, blocks 422, pages 423; abstract). The flash cache storage is divided into blocks, each of which is an erase unit divided into the same number of pages; accordingly, each cache block in the cache array has a same size;
selecting a cache block for storing the message according to a size of the message to be stored and a number of free addresses of each cache block; and (Fig. 8, logical pages 411, physical pages 423; Fig. 9, steps S103 and S106; ¶ 118). Either an existing cache block storing a same attribute as data, or an empty block is selected, and the size of the data is compared to the number of free pages (addresses) in the selected block. If there is insufficient space, then additional blocks may be selected to fit the data. (Fig. 9, steps S103 and S106). The physical pages correspond to logical pages, which in turn are divided into, for example, 8 block addresses each (Fig. 8, logical pages 411, physical pages 423; ¶ 118);
storing the message in a free address of a selected cache block (Fig. 9, steps S104 and S107). Ogawa discloses caching data of a write request (a message) in the selected cache block.
Ogawa discloses the limitations above; however, some of the elements are described in different figures, and it is unclear whether they are all part of the same embodiment; nevertheless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine the elements of Ogawa into a single embodiment, because it would be obvious to make the elements integral (MPEP § 2144.04(V)(B).
Re claim 13, Ogawa discloses the method of claim 1 above; accordingly, it also discloses an electronic equipment implementing that method, as in claim 13 (¶ 213). Further, Ogawa discloses the following:
at least one processor (¶ 213). The method may be implemented using a processor;
a memory communicating with the at least one processor (¶ 213). The processor communicates with a computer-readable storage medium (memory);
wherein the memory stores an instruction executable by the at least one processor, and the instruction is executed by the at least one processor to make the at least one processor execute a method for caching a message comprising (¶ 213). The computer-readable medium (memory) stores a program (instructions) to cause the processor to execute the method.
Re claim 14, Ogawa discloses the method of claim 1 above; accordingly, it also discloses a non-transitory computer-readable storage medium, storing a computer program, wherein when the computer program is executed by a processor, executes that method, as in claim 14 (¶ 213).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ogawa in view of Hsieh et al (US 7088872 B1), further in view of Jaiswal et al (US 2018/0060145 A1).
Re claim 7, Ogawa discloses the method of claim 1, and further discloses storing the message according to the size of the message to be stored and the number of free addresses of each block the method further comprises […] the selecting the cache block for storing the message according to the size of the message to be stored and the number of free addresses of each cache block comprises: selecting the cache block for storing the message from the cache array […] according to the size of the message and the number of free addresses of each cache block (Fig. 8, logical pages 411, physical pages 423; Fig. 9, steps S103 and S106; ¶ 118), but does not explicitly disclose a single-port RAM, or dequeueing.
Hsieh discloses that the cache block is the single-port RAM (col. 8, lines 41-47). The cache (cache block) may be implemented as a single-port RAM.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the cache of Ogawa to utilize a single-port RAM, as in Hsieh, because Hsieh suggests that using a single-port RAM substantially reduces silicon cost and power consumption over more sophisticated cache designs such as dual-port cache RAM (col. 8, lines 41-47).
Jaiswal discloses before the selecting the cache block for storing the message […] determining whether a dequeued message exists in the cache array; in response to that the dequeued message exists in the cache array, removing a cache block where the dequeued message is located from the cache array; and […] selecting the cache block for storing the message from the cache array after the cache block is removed (Fig. 3A; ¶ 2). This limitation is indefinite, as noted above. Examiner interprets it to mean determining whether to dequeue a message from the cache to free up space for future enqueued messages. The cache operates as a message queue, with messages being enqueued and dequeued in a first-in-first-out order. Accordingly, messages to be dequeued (dequeued messages) are located and removed from the cache, in order to make room for subsequent (after) enqueued messages (the message).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the method of Ogawa (combined with Hsieh) to utilize an enqueueing/dequeueing message cache, as in Jaiswal, because Jaiswal suggests that a message cache provides a fast in-memory access path to all queueing functionality including enqueue operations, dequeue operations, and notification operations, it enables enqueuers/dequeuers to avoid scan or sort structures, such as database tables, and the queue operations have no disk latency (¶ 37).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Peddada et al (US 6295068 B1). Utilizes a best-fit algorithm to search available cache blocks to find a block with sufficient free space to store data, and stores it (col. 7, lines 34-52).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/ Primary Examiner, Art Unit 2132