DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 3, 2025 is in compliance with the provisions of 37 CFR 1.97. However, NPL document No. 005 is not in compliance with 37 CFR 1.98(a)(1) for the reason below and have not been considered.
For NPL document No. 005, the date of publication (month and year) is not listed. As set forth in MPEP 609.04(a), “[the] date of publication supplied must include at least the month and year of publication, except that the year of publication (without the month) will be accepted if the application points out in the information disclosure statement that the year of publication is sufficiently earlier than the effective U.S. filing date and any foreign priority date so that the particular month of publication is not in issue.” The date of publication submitted in the IDS does not include the month, and applicant has not pointed out in the IDS that the year of publication is sufficiently earlier than the effective U.S. filing date and any foreign priority date so that the particular month of publication is not in issue. Therefore, NPL document No. 005 is not in compliance with 37 CFR 1.98(a)(1) and has not been considered.
Applicant may file a new information disclosure statement or correct the deficiency in the previously filed IDS, but the date that the new IDS or correction is filed will be the date of the IDS for purposes of determining compliance with the requirements based on the time of filing of the IDS (37 CFR 1.97). See MPEP 609.05(a).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-18 of U.S. Patent 10,296,236 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-20 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent 10,296,236. Although the claims at issue are not identical, they are not patentably distinct from each other because the teachings of claim 1, claim 2, claim 5, claim 8, claim 9, claim 10, claim 13, claim 16, claim 17 and claim 18 of the instant application can be found in the teachings of claim 1, claim 7 and claim 13 of U.S. Patent 10,296,236, the teachings of claim 3, claim 11, and claim 19 of the instant application can be found in the teachings of claim 2, claim 8, and claim 14 of U.S. Patent 10,296,236, the teachings of claim 4, claim 12, and claim 20 of the instant application can be found in the teachings of claim 3, claim 9, and claim 15 of U.S. Patent 10,296,236, the teachings of claim 6 and claim 14 of the instant application can be found in the teachings of claim 5, claim 11, and claim 17 of U.S. Patent 10,296,236, and the teachings of claim 7 and claim 15 of the instant application can be found in the teachings of claim 6, claim 12, and claim 18 of U.S. Patent 10,296,236.
Claims 1, 8 and 15 of U.S. Patent 11,385,801 contains every element of claims 1, 9 and 17 of the instant application and as such anticipates claims 1, 9 and 17 of the instant application.
Claims 1, 9 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8 and 15 of U.S. Patent No. 11,385,801. Although the claims at issue are not identical, they are not patentably distinct from each other because the teachings of claim 1, 9 and 17 of the instant application can be found in the teachings of claim 1, 8 and 15 of U.S. Patent No. 11,385,801.
Claims 1-20 of U.S. Patent 12,175,091 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-20 of the instant application.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent 12,175,091. Although the claims at issue are not identical, they are not patentably distinct from each other because the teachings of claim 1, claim 9 and claim 17 of the instant application can be found in the teachings of claim 1, claim 2, claim 9, claim 10, claim 17 and claim 18 of U.S. Patent 12,175,091, the teachings of claim 2, claim 10, and claim 18 of the instant application can be found in the teachings of claim 2, claim 10, and claim 18 of U.S. Patent 12,175,091, the teachings of claim 3, claim 11, and claim 19 of the instant application can be found in the teachings of claim 3, claim 11, and claim 19 of U.S. Patent 12,175,091, the teachings of claim 4, claim 12, and claim 20 of the instant application can be found in the teachings of claim 4, claim 12, and claim 20 of U.S. Patent 12,175,091, the teachings of claim 5 and claim 13 of the instant application can be found in the teachings of claim 5, and claim 13 of U.S. Patent 12,175,091, the teachings of claim 6 and claim 14 of the instant application can be found in the teachings of claim 6 and claim 14 of U.S. Patent 12,175,091, the teachings of claim 7 and claim 15 of the instant application can be found in the teachings of claim 7 and claim 15 of U.S. Patent 12,175,091, and the teachings of claim 8 and claim 16 of the instant application can be found in the teachings of claim 8 and claim 16 of U.S. Patent 12,175,091.
Claims 2, 10 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8 and 15 of U.S. Patent No. 11,385,801 in view of in view of Chow et al. (hereinafter Chow, US Publication No. 2003/0225961).
Regarding claim 2, Chow teaches:
The method of claim 1, wherein the state information is included within the control information, further comprising performing, in dependence upon the control information (See Fig. 2 Bad Block List. [0041] “The bad block detection mechanism maintains a list of all defective blocks, and adds failing blocks to the bad block list when they are detected. A separate bad block list can be maintained for each flash bank in the system. When a block is determined to be defective, it is added to the bad block list, thus it is no longer available to be used.” Under broadest reasonable interpretation, the control information of corresponds to the bad block list information described in Chow.), a storage device management operation (Fig. 2, Block List. [0051] “The bad block list informs the system which blocks are usable and which blocks should not be used for storing data.” [0034] “The block list is an ordered list of all non-defective, user blocks in the system. The blocks in the block list are those that are available for use by the user of the flash memory management system. This list is essentially static, with changes occurring only when a block is removed because it has become defective.” Requests are sent to a block in the Block List of Fig. 2 (target memory block), based on information recorded in the bad block list.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the offloading management system of U.S. Patent No. 11,385,801 with the flash memory management system method of Chow to prolong the service life of memory devices by improving wear leveling operations in the memory system.
Claim 10 and claim 18 are rejected for the same reasons as claim 2.
Claims 3-4, 7, 11-12, 15 and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-3, 6, 9-10, 13, 16-17 and 20 of U.S. Patent No. 11,385,801 in view of in view of Chow et al. (hereinafter Chow, US Publication No. 2003/0225961).
Regarding claim 3, U.S. Patent No. 11,385,801 teaches:
the control information includes a bad block list, the bad block list including information describing memory blocks on the storage device that have failed (See claim 2 of U.S. Patent No. 11,385,801 “wherein: the control information includes a bad block list, the bad block list including information describing memory blocks on the storage device that have failed.”); and
U.S. Patent No. 11,385,801 does not explicitly disclose what Chow teaches:
The method of claim 2 further comprising receiving a request to write data to the storage device ([0028] “These blocks are candidates for selection when the user application requests a write operation.” [0029] “for any block request the smallest erase count block will be returned”), wherein:
performing the storage device management operation includes:
identifying a target memory block on the storage device that is not on the bad block list (Fig. 2, Block List. [0034] “The block list is an ordered list of all non-defective, user blocks in the system. The blocks in the block list are those that are available for use by the user of the flash memory management system. This list is essentially static, with changes occurring only when a block is removed because it has become defective.” Blocks in the Block List of Fig. 2 are not in the Bad Block List of Fig. 2, as the Block List contains non-defective blocks and the Bad Block List contains defective blocks.); and
sending a request to write the data to the target memory block (Fig. 2, Block List. [0051] “The bad block list informs the system which blocks are usable and which blocks should not be used for storing data.” [0034] “The block list is an ordered list of all non-defective, user blocks in the system. The blocks in the block list are those that are available for use by the user of the flash memory management system. This list is essentially static, with changes occurring only when a block is removed because it has become defective.” Requests are sent to a block in the Block List of Fig. 2 (target memory block).).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the offloading management system of U.S. Patent No. 11,385,801 with the flash memory management system method of Chow to prolong the service life of memory devices by improving wear leveling operations in the memory system.
Regarding claim 4, U.S. Patent No. 11,385,801 teaches:
the control information includes a program-erase ('P/E') count for each memory block, the P/E count including information describing a number of times that data has been written to and erased from a particular memory block (See claim 3 of U.S. Patent No. 11,385,801 “wherein: the control information includes a program-erase (‘P/E’) count for each memory block, the P/E count including information describing a number of times that data has been written to and erased from a particular memory block.”); and
U.S. Patent No. 11,385,801 does not explicitly disclose what Chow teaches:
The method of claim 2 further comprising receiving a request to write data to the storage device ([0028] “These blocks are candidates for selection when the user application requests a write operation.” [0029] “for any block request the smallest erase count block will be returned”), wherein:
performing the storage device management operation includes:
identifying a target memory block on the storage device that is associated with a lowest P/E count ([0029] “The free block mechanism selects blocks from the free block list based on the erase count. Selecting the memory block that has the smallest erase count will optimize wear leveling among all memory blocks. So, although the free block list is unsorted and remains so, for any block request the smallest erase count block will be returned for a given window size.” [0030] “The search routine then searches the window portion of the free block list for the flash memory block with the lowest erase count.”); and
sending a request to write the data to the target memory block ([0012] “The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing.” [0029] “for any block request the smallest erase count block will be returned”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the offloading management system of U.S. Patent No. 11,385,801 with the flash memory management system method of Chow to prolong the service life of memory devices by improving wear leveling operations in the memory system.
Regarding claim 7, U.S. Patent No. 11,385,801 teaches:
The method of claim 2 wherein:
the control information includes error correction status information for one or more memory blocks (See claim 6 of U.S. Patent No. 11,385,801 “the control information includes error correction status information for one or more memory blocks.”); and
U.S. Patent No. 11,385,801 does not explicitly disclose what Chow teaches:
performing the storage device management operation includes:
determining whether the error correction status information exceeds a damage threshold ([0047] “In another implementation, a hardware error counter is maintained for each flash block to keep a combined count of flash read and write errors. When the hardware error counter reaches a certain threshold, the block is considered defective and all valid data is migrated.”); and
responsive to determining that the error correction status information exceeds the damage threshold:
identifying damaged data; and
storing a copy of the damaged data at a new location ([0047] “When the hardware error counter reaches a certain threshold, the block is considered defective and all valid data is migrated.” Hardware error counter/threshold may be determined by EDAC errors, see [0047].).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the offloading management system of U.S. Patent No. 11,385,801 with the flash memory management system method of Chow to prolong the service life of memory devices by improving wear leveling operations in the memory system.
Claim 11 and claim 19 are rejected for the same reasons as claim 3. Claim 12 and claim 20 are rejected for the same reasons as claim 4. Claim 7 is rejected for the same reasons as claim 15. See mirrored claims 9-10, 16-17, 13 and 20 of U.S. Patent No. 11,385,801 which correspond to claims 11-12, 19-20 and 15 of the instant application respectively.
Claims 8 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 11,385,801 in view of Yamamoto (US Publication No. 2013/0067152).
Regarding claim 8, Yamamoto teaches:
The method of claim 1 wherein the storage system controller is coupled with a plurality of storage devices and each storage device is coupled for data communications with the storage system controller over one or more data communications fabrics, wherein the storage device includes a storage device controller (See claim 1 of Yamamoto “A storage system, comprising: a storage controller; a plurality of flash memory devices coupled to the storage controller, each of the flash memory devices including a flash memory controller and a plurality of flash memory chips,” Yamamoto teaches a flash memory device to include a flash memory controller.)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide a flash memory device (as described in U.S. Patent No. 11,385,801) that includes a flash memory controller (as described in Yamamoto) to allow the flash memory to manage the data stored on NOR and NAND flash memory (such as I/O operations) and communicate with the computer or host. A flash controller may also be used to maps flash cells and determine which spare cells will replace any failed ones, thereby providing overall data management and configurations for the flash memory.
Claim 16 is rejected for the same reasons as claim 8.
Claims 5 and 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4, 11 and 18 of U.S. Patent No. 11,385,801 in view of Jeddeloh et al. (hereinafter Jeddeloh, US Publication No. 2010/0250826).
Regarding claim 5, U.S. Patent No. 11,385,801 teaches:
the control information includes information identifying a plurality of memory access channels and a range of memory addresses associated with each memory access channel (See claim 4 of U.S. Patent No. 11,385,801 “wherein: the control information includes information identifying a plurality of memory access channels and a range of memory addresses associated with each memory access channel.”); and
U.S. Patent No. 11,385,801 does not explicitly disclose what Jeddeloh teaches:
The method of claim 2 further comprising receiving a request to write data to the storage device (Fig. 4, block 402. See [0043].), wherein:
performing the storage device management operation includes:
identifying a target memory block on the storage device, including selecting a memory channel; and
sending a request to write the data to the target memory block (Fig. 4, block 402. See [0029] “With multiple parallel channels in the drive, decisions can be made for writing to the device on the basis of bandwidth. For example, write commands issued by the host (e.g., through a memory access device) may be routed to a channel or channels that are not in heavy current use.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the offloading management system of U.S. Patent No. 11,385,801 with the multi-channel system of Jeddeloh to increase bandwidth and reduce latency by allowing parallel processing of memory requests.
Claim 13 is rejected for the same reasons as claim 5. See mirrored claims 11 and 18 of U.S. Patent No. 11,385,801 which correspond to claim 13 of the instant application.
Claims 6 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5, 12 and 19 of U.S. Patent No. 11,385,801 in view of Dancho et al. (hereinafter Dancho, US Patent No. 2015/0113203).
Regarding claim 6, U.S. Patent No. 11,385,801 teaches:
the control information includes information identifying a plurality of memory dies and a range of memory addresses associated with each memory die (See claim 5 of U.S. Patent No. 11,385,801 “wherein: the control information includes information identifying a plurality of memory dies and a range of memory addresses associated with each memory die.”); and
U.S. Patent No. 11,385,801 does not explicitly disclose what Dancho teaches:
The method of claim 2 further comprising receiving a request to write data to the storage device (Fig. 7, block 706, “in response to a write command” [0069] “storage controller 120 receives a host write command”), wherein:
performing the storage device management operation includes:
identifying a target memory block on the storage device, including selecting a target memory die; and
sending a request to write the data to the target memory block (Fig. 6A block 612, block 614, and block 616. [0071] “selection module 222 selects a die group comprising highly ranked die for write operations.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the offloading management system of U.S. Patent No. 11,385,801 with the die management method of Dancho to improve nonvolatile memory endurance by essentially implementing wear-leveling techniques at the memory die level.
Claim 14 is rejected for the same reasons as claim 6. See mirrored claims 12 and 19 of U.S. Patent No. 11,385,801 which correspond to claim 14 of the instant application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 8-10 and 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Haas et al. (Hereinafter Haas, US Publication No. 2011/0131231).
Regarding claim 1, Haas teaches:
A method comprising:
retrieving, from a storage device by an external storage system controller (See Figure 1, in which the flash controller 104 is external to the flash memory array 102.), state information located by the storage device that is usable in performing a storage device management operation for the storage device (See [0025] “the controller 104 sequentially places the checkpoints with time stamps to allow for fast recovery of metadata.” See [0028] “With the method described above, the most recent checkpoint can be located in an efficient manner through the easy-to-apply rules described above. The checkpoint located holds the key information about the metadata that has been written most recently. Therefore, key information, such as the root of the LBA to PBA mapping tables, can be identified by the last checkpoint written before the device was powered down.” See [0029] “FIG. 3 illustrates a flow diagram of a method for efficiently locating metadata structures in flash memory devices implemented by the controller 104 in accordance with one exemplary embodiment.” See [0029] “If the answer is yes, the youngest checkpoint is found at block 312. As such, relevant metadata structures can be read.” The controller 104 retrieves (i.e. recovers, identifies, etc.) the key information (i.e. state information) from the metadata structure stored in the flash memory.).
performing, by the storage system controller, the storage device management operation using the state information obtained from the storage device (See [0033] “In accordance with one embodiment, a block maintenance strategy is performed by the controller 104 to ensure that checkpoints can be written on the device and written uniformly over the whole storage capacity. In other words, the block maintenance strategy ensures that there are pages in a certain range in which checkpoints can be written in the device in advance so that future checkpoints can be written in an orderly and uniform manner enabling for the checkpoint localization algorithm described above to perform as intended. The flash memory system described herein implements a garbage collection algorithm or other algorithm used to free up blocks within a flash-based memory device, such as flash memory device 100. The free blocks are maintained in a free block queue, which is separated into two different queues in accordance with one embodiment. In accordance with one embodiment, one queue, referred to as the normal free queue (NFQ), is consumed by normal writes while the other queue, referred to as the checkpoint free queue (CPFQ) is consumed by checkpoint metadata writes.” See claim 5 of Haas “The method of claim 4, wherein blocks freed by the garbage collection process are maintained by placing freed blocks with any page outside an interval in a first queue and placing freed blocks with a page on the interval in a second queue.”).
Regarding claim 2, Haas teaches:
The method of claim 1, wherein the state information is included within the control information, further comprising performing, in dependence upon the control information, a storage device management operation (See [0033] “In accordance with one embodiment, a block maintenance strategy is performed by the controller 104 to ensure that checkpoints can be written on the device and written uniformly over the whole storage capacity. In other words, the block maintenance strategy ensures that there are pages in a certain range in which checkpoints can be written in the device in advance so that future checkpoints can be written in an orderly and uniform manner enabling for the checkpoint localization algorithm described above to perform as intended. The flash memory system described herein implements a garbage collection algorithm or other algorithm used to free up blocks within a flash-based memory device, such as flash memory device 100. The free blocks are maintained in a free block queue, which is separated into two different queues in accordance with one embodiment. In accordance with one embodiment, one queue, referred to as the normal free queue (NFQ), is consumed by normal writes while the other queue, referred to as the checkpoint free queue (CPFQ) is consumed by checkpoint metadata writes.” See claim 5 of Haas “The method of claim 4, wherein blocks freed by the garbage collection process are maintained by placing freed blocks with any page outside an interval in a first queue and placing freed blocks with a page on the interval in a second queue.”).
Regarding claim 8, Haas teaches:
The method of claim 1 wherein the storage system controller is coupled with a plurality of storage devices and each storage device is coupled for data communications with the storage system controller over one or more data communications fabrics, wherein the storage device includes a storage device controller (See Figure 1. See abstract.).
Claim 9 and claim 17 are rejected for the same reasons as claim 1. Claim 10 and claim 18 are rejected for the same reasons as claim 2. Claim 16 is rejected for the same reasons as claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 7, 11-12, 15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Haas in view of Chow et al. (hereinafter Chow, US Publication No. 2003/0225961).
Haas does not teach the limitations of claim 3.
Regarding claim 3, Chow teaches:
The method of claim 2 further comprising receiving a request to write data to the storage device ([0028] “These blocks are candidates for selection when the user application requests a write operation.” [0029] “for any block request the smallest erase count block will be returned”), wherein:
the control information includes a bad block list, the bad block list including information describing memory blocks on the storage device that have failed (See Fig. 2 Bad Block List. [0041] “The bad block detection mechanism maintains a list of all defective blocks, and adds failing blocks to the bad block list when they are detected. A separate bad block list can be maintained for each flash bank in the system. When a block is determined to be defective, it is added to the bad block list, thus it is no longer available to be used.”); and
performing the storage device management operation includes:
identifying a target memory block on the storage device that is not on the bad block list (Fig. 2, Block List. [0034] “The block list is an ordered list of all non-defective, user blocks in the system. The blocks in the block list are those that are available for use by the user of the flash memory management system. This list is essentially static, with changes occurring only when a block is removed because it has become defective.” Blocks in the Block List of Fig. 2 are not in the Bad Block List of Fig. 2, as the Block List contains non-defective blocks and the Bad Block List contains defective blocks.); and
sending a request to write the data to the target memory block (Fig. 2, Block List. [0051] “The bad block list informs the system which blocks are usable and which blocks should not be used for storing data.” [0034] “The block list is an ordered list of all non-defective, user blocks in the system. The blocks in the block list are those that are available for use by the user of the flash memory management system. This list is essentially static, with changes occurring only when a block is removed because it has become defective.” Requests are sent to a block in the Block List of Fig. 2 (target memory block).).
In the combination of Haas and Chow, Haas is being modified to include the specific state/control information (i.e. bad block list) of Chow to be used as the state/control information described in Haas when performing a storage device management operation. Such combination would result in the bad block information described in claim 3 to be retrieved/stored for use. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the memory system of Haas with the flash memory management system method of Chow to prolong the service life of memory devices by improving wear leveling operations in the memory system.
Haas does not teach the limitations of claim 4.
Regarding claim 4, Chow teaches:
The method of claim 2 further comprising receiving a request to write data to the storage device ([0028] “These blocks are candidates for selection when the user application requests a write operation.” [0029] “for any block request the smallest erase count block will be returned”), wherein:
the control information includes a program-erase ('P/E') count for each memory block, the P/E count including information describing a number of times that data has been written to and erased from a particular memory block ([0029] “for any block request the smallest erase count block will be returned.” [0048] “The flash status mechanism stores information in a flash status table that describes the content and status of the data in the flash disk. The flash status table is a data structure that describes the status of each flash block in the system. It can contain such information as…block's erase count.” [0049] “The information in the flash status table is used by the free block mechanism to facilitate wear leveling.”); and
performing the storage device management operation includes:
identifying a target memory block on the storage device that is associated with a lowest P/E count ([0029] “The free block mechanism selects blocks from the free block list based on the erase count. Selecting the memory block that has the smallest erase count will optimize wear leveling among all memory blocks. So, although the free block list is unsorted and remains so, for any block request the smallest erase count block will be returned for a given window size.” [0030] “The search routine then searches the window portion of the free block list for the flash memory block with the lowest erase count.”); and
sending a request to write the data to the target memory block ([0012] “The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing.” [0029] “for any block request the smallest erase count block will be returned”).
In the combination of Haas and Chow, Haas is being modified to include the specific state/control information (i.e. p/e information) of Chow to be used as the state/control information described in Haas when performing a storage device management operation. Such combination would result in the p/e information described in claim 4 to be retrieved/stored for use. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the memory system of Haas with the flash memory management system method of Chow to prolong the service life of memory devices by improving wear leveling operations in the memory system.
Haas does not teach the limitations of claim 7.
Regarding claim 7, Chow teaches:
The method of claim 2 wherein:
the control information includes error correction status information for one or more memory blocks ([0043] “The preferred implementation of the detection mechanism examines errors that are recorded by an Error Detection and Correction (EDAC) system and certain error statuses on writes and erases. These errors can include correctable EDAC errors observed when reading a page, uncorrectable EDAC errors while reading a page, flash device errors (FDE) while writing a page, and any error that occurs while erasing a block.”); and
performing the storage device management operation includes:
determining whether the error correction status information exceeds a damage threshold ([0047] “In another implementation, a hardware error counter is maintained for each flash block to keep a combined count of flash read and write errors. When the hardware error counter reaches a certain threshold, the block is considered defective and all valid data is migrated.”); and
responsive to determining that the error correction status information exceeds the damage threshold:
identifying damaged data; and
storing a copy of the damaged data at a new location ([0047] “When the hardware error counter reaches a certain threshold, the block is considered defective and all valid data is migrated.” Hardware error counter/threshold may be determined by EDAC errors, see [0047].).
In the combination of Haas and Chow, Haas is being modified to include the specific state/control information (i.e. error correction status information) of Chow to be used as the state/control information described in Haas when performing a storage device management operation. Such combination would result in the error correction status information described in claim 7 to be retrieved/stored for use. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the memory system of Haas with the flash memory management system method of Chow to prolong the service life of memory devices by improving wear leveling operations in the memory system.
Claim 11 and claim 19 are rejected for the same reasons as claim 3. Claim 12 and claim 20 are rejected for the same reasons as claim 4. Claim 7 is rejected for the same reasons as claim 15.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Haas in view of Jeddeloh et al. (hereinafter Jeddeloh, US Publication No. 2010/0250826).
Haas does not teach the limitations of claim 5.
Regarding claim 5, Jeddeloh teaches:
The method of claim 2 further comprising receiving a request to write data to the storage device (Fig. 4, block 402. See [0043].), wherein:
the control information includes information identifying a plurality of memory access channels and a range of memory addresses associated with each memory access channel ([0042] “The host is provided the relationship between the logical and physical address translation contained in the LBA. Each channel, for example, can be allocated to a certain range of logical addresses, and any logical address within the range is assigned to that physical channel.” [0037] “Embodiments of the invention can address read variability in SSDs by creating individual drives for each flash channel. The flash channels can then be dedicated to reads or writes. The LBA tables are created such that there is a logical to physical relationship between each channel and a logical address range.”); and
performing the storage device management operation includes:
identifying a target memory block on the storage device, including selecting a memory channel; and
sending a request to write the data to the target memory block (Fig. 4, block 402. See [0029] “With multiple parallel channels in the drive, decisions can be made for writing to the device on the basis of bandwidth. For example, write commands issued by the host (e.g., through a memory access device) may be routed to a channel or channels that are not in heavy current use.).
In the combination of Haas and Jeddeloh, Haas is being modified to include the specific state/control information (i.e. memory channel access information) of Jeddeloh to be used as the state/control information described in Haas when performing a storage device management operation. Such combination would result in the memory channel access information described in claim 5 to be retrieved/stored for use. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the memory system of Haas with the multi-channel system of Jeddeloh to increase bandwidth and reduce latency by allowing parallel processing of memory requests.
Claim 13 is rejected for the same reasons as claim 5.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Haas in view of Dancho et al. (hereinafter Dancho, US Patent No. 2015/0113203).
Haas does not teach the limitations of claim 6.
Regarding claim 6, Dancho teaches:
The method of claim 2 further comprising receiving a request to write data to the storage device (Fig. 7, block 706, “in response to a write command” [0069] “storage controller 120 receives a host write command”), wherein:
the control information includes information identifying a plurality of memory dies and a range of memory addresses associated with each memory die (See Fig. 5, [0061] “FIG. 5 is a diagram of a die group mapping corresponding to the plurality of die groups in FIG. 4 in accordance with some embodiments. In some embodiments, die group mapping 220 is stored in storage controller memory and includes the logical address (or range of logical addresses, or a representation thereof) for die assigned to each die group. In FIG. 5, die group mapping 220 associates the logical address (or range of logical addresses) for all die in channels 0-15 with their assigned die groups. In FIG. 5, the logical addresses for die 3 and 7 in channel 0 (e.g., logical addresses 504 and 506, respectively) are included in entry 502 associated with die group 0.” Also, see Fig. 6A, block 606 and block 608.); and
performing the storage device management operation includes:
identifying a target memory block on the storage device, including selecting a target memory die; and
sending a request to write the data to the target memory block (Fig. 6A block 612, block 614, and block 616. [0071] “selection module 222 selects a die group comprising highly ranked die for write operations.”).
In the combination of Haas and Dancho, Haas is being modified to include the specific state/control information (i.e. memory die information) of Dancho to be used as the state/control information described in Haas when performing a storage device management operation. Such combination would result in the memory die information described in claim 6 to be retrieved/stored for use. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the memory system of Haas with the die management method of Dancho to improve nonvolatile memory endurance by essentially implementing wear-leveling techniques at the memory die level.
Claim 14 is rejected for the same reasons as claim 6.
Conclusion
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/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139