Prosecution Insights
Last updated: April 19, 2026
Application No. 19/000,250

CURRENT MODE CONTROL TYPE SWITCHING POWER SUPPLY DEVICE

Non-Final OA §103§DP
Filed
Dec 23, 2024
Examiner
CHOWDHURI, SWARNA N
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co. Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
98%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
258 granted / 340 resolved
+7.9% vs TC avg
Strong +22% interview lift
Without
With
+21.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
31 currently pending
Career history
371
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
59.6%
+19.6% vs TC avg
§102
24.7%
-15.3% vs TC avg
§112
12.1%
-27.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 340 resolved cases

Office Action

§103 §DP
25DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Current Application (19000250) US Patent NO. 12214676 1. A switching power supply device comprising: a controller configured to generate a first gate signal and a second gate signal to control a first switch to which an input voltage is applied and a second switch connected to the first switch; a current sense portion configured to sense a signal based on an on-resistance of the second switch; a charging switch configured to be connected to the current sense portion and configured to, when the second switch is an on state, control charging of a capacitor according to the signal based on the on-resistance of the second switch; and an accumulating portion including the capacitor configured to connect to the charging switch and configured to accumulate information according to the signal based on the on-resistance of the second switch, wherein the controller controls off timing of the first switch based on a first voltage, a feedback voltage corresponding to an output voltage of the switching power supply device, and a reference voltage, the first voltage being a voltage reflecting the information accumulated by the accumulating portion. 2. The switching power supply device according to claim 1, wherein the controller includes an error amplifier configured to amplify a difference voltage between the feedback voltage and the reference voltage. 1. A switching power supply device comprising: a first switch having a first terminal connected to an application terminal to which an input voltage is applied; a second switch having a first terminal connected to a second terminal of the first switch and a second terminal connected to an application terminal to which a voltage lower than the input voltage is applied; a controller configured to control the first switch and the second switch; a current sense portion configured to sense a signal based on an on-resistance of the second switch; a charging switch configured to be connected to the current sense portion and configured to, when the second switch is on, control charging of a capacitor according to the signal based on the on-resistance of the second switch; and an accumulating portion including the capacitor configured to connect to the charging switch and configured to accumulate information according to the signal based on the on-resistance of the second switch, wherein the controller includes an error amplifier configured to amplify a difference between a voltage corresponding to an output voltage of the switching power supply device and a reference voltage, and the controller controls off timing of the first switch based on a first voltage and an output voltage of the error amplifier, the first voltage being a voltage reflecting the information accumulated by the accumulating portion. 3. The switching power supply device according to claim 1, wherein the controller includes: a comparator configured to compare the first voltage with the output voltage of the error amplifier so as to generate a reset signal as a comparison signal; an oscillator configured to generate a set signal as a clock signal of a predetermined frequency; and a timing control circuit configured to control on and off states of the first switch and on and off states of the second switch in accordance with the set signal and the reset signal. 8. The switching power supply device according to claim 7, wherein the controller includes: a comparator configured to compare the first voltage with the output voltage of the error amplifier so as to generate a reset signal as a comparison signal; an oscillator configured to generate a set signal as a clock signal of a predetermined frequency; and a timing control circuit configured to control on and off states of the first switch and on and off states of the second switch in accordance with the set signal and the reset signal. 2. The switching power supply device according to claim 1, wherein the controller includes: a comparator configured to compare the first voltage with the output voltage of the error amplifier so as to generate a reset signal as a comparison signal; an oscillator configured to generate a set signal as a clock signal of a predetermined frequency; and a timing control circuit configured to control on and off of the first switch and on and off of the second switch in accordance with the set signal and the reset signal. 4. The switching power supply device according to claim 1, wherein the controller controls the first switch and the second switch in accordance with the current sensed by the current sensing portion. 9. The switching power supply device according to claim 8, wherein the controller controls the first switch and the second switch in accordance with the current sensed by the current sensing portion. 3. The switching power supply device according to claim 1, wherein the controller controls the first switch and the second switch in accordance with the current sensed by the current sensing portion. 5. The switching power supply device according to claim 1, wherein the second switch is a MOS transistor, and the current sensing portion senses the current flowing in the second switch by using a voltage between both ends of an on resistor of the MOS transistor. 10. The switching power supply device according to claim 9, wherein the second switch is a MOS transistor, and the current sensing portion senses the current flowing in the second switch by using a voltage between both ends of an on resistor of the MOS transistor. 4. The switching power supply device according to claim 1, wherein the second switch is a MOS transistor, and the current sensing portion senses the current flowing in the second switch by using a voltage between both ends of an on resistor of the MOS transistor. 6. A switching power supply device comprising: a controller configured to generate a first gate signal and a second gate signal to control a first switch to which an input voltage is applied and a second switch connected to the first switch; a current sense portion configured to sense a signal based on an on-resistance of the second switch; a charging switch configured to be connected to the current sense portion and configured to, when the second switch is on, control charging of a capacitor according to the signal based on the on-resistance of the second switch; and an accumulating portion configured to connect to the charging switch and configured to accumulate information according to the signal based on the on-resistance of the second switch, wherein the controller controls off timing of the first switch based on a first voltage, a feedback voltage corresponding to an output voltage of the switching power supply device, and a reference voltage, the first voltage being based on the current flowing in the second switch when the first switch is an off state and the second switch is an on state. 7. The switching power supply device according to claim 6, wherein the controller includes an error amplifier configured to amplify a difference voltage between the feedback voltage and the reference voltage. 5. An integrated circuit comprising: a controller configured to control: a first switch having a first terminal connected to an application terminal to which an input voltage is applied, and a second switch having a first terminal connected to a second terminal of the first switch and a second terminal connected to an application terminal to which a voltage lower than the input voltage is applied; a current sense portion configured to sense a signal based on an on-resistance of the second switch; a charging switch configured to be connected to the current sense portion and configured to, when the second switch is on, control charging of a capacitor according to the signal based on the on-resistance of the second switch; and an accumulating portion including the capacitor configured to connect to the charging switch and configured to accumulate information according to the signal based on the on-resistance of the second switch, wherein the controller includes an error amplifier configured to amplify a difference between a voltage corresponding to an output voltage of a switching power supply device and a reference voltage, and the controller controls off timing of the first switch based on a first voltage and an output voltage of the error amplifier, the first voltage being a voltage reflecting the information accumulated by the accumulating portion. 11. In-vehicle equipment comprising the switching power supply device according to claim 1. 6. In-vehicle equipment comprising the switching power supply device according to claim 1. 11. In-vehicle equipment comprising the switching power supply device according to claim 1. 7. In-vehicle equipment comprising the switching power supply device according to claim 2. 11. In-vehicle equipment comprising the switching power supply device according to claim 1. 8. In-vehicle equipment comprising the switching power supply device according to claim 3. 11. In-vehicle equipment comprising the switching power supply device according to claim 1. 9. In-vehicle equipment comprising the switching power supply device according to claim 4. 13. In-vehicle equipment comprising the switching power supply device according to claim 6. 10. In-vehicle equipment comprising the integrated circuit according to claim 5. 12. A vehicle comprising: the in-vehicle equipment according to claim 11; and a battery configured to supply electric power to the in-vehicle equipment. 11. A vehicle comprising: the in-vehicle equipment according to claim 6; and a battery configured to supply electric power to the in-vehicle equipment. 12. A vehicle comprising: the in-vehicle equipment according to claim 11; and a battery configured to supply electric power to the in-vehicle equipment. 12. A vehicle comprising: the in-vehicle equipment according to claim 7; and a battery configured to supply electric power to the in-vehicle equipment. 14. A vehicle comprising: the in-vehicle equipment according to claim 13; and a battery configured to supply electric power to the in-vehicle equipment. 13. A vehicle comprising: the in-vehicle equipment according to claim 8; and a battery configured to supply electric power to the in-vehicle equipment. 14. A vehicle comprising: the in-vehicle equipment according to claim 13; and a battery configured to supply electric power to the in-vehicle equipment. 14. A vehicle comprising: the in-vehicle equipment according to claim 9; and a battery configured to supply electric power to the in-vehicle equipment. 14. A vehicle comprising: the in-vehicle equipment according to claim 13; and a battery configured to supply electric power to the in-vehicle equipment. 15. A vehicle comprising: the in-vehicle equipment according to claim 10; and a battery configured to supply electric power to the in-vehicle equipment. Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12214676. Claims 1-14 of the current application is not patently distinct from the earlier patent claims 1-15 and as such is unpatentable for obvious-type double patenting. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0336857 (Liu) in view of US 2014/0160601 (Ouyang). Regarding claim 1, Liu teaches a switching power supply device (Fig. 1 shows switching power supply device) [0024] comprising: a controller (Fig. 1 shows switching controller comprising switching control device U3) configured to generate a first gate signal and a second gate signal (Fig. 1 shows switching control device U3 configured to generate a first switching control signal and a second switching control signal) [0028] to control a first switch to which an input voltage is applied (Fig. 1 shows first switch M1 is controlled by switching control signal from U3 to receive an input voltage Vin) [0024-25] and a second switch connected to the first switch (Fig. 1 shows second switch M2 electrically connected to first switch M1) [0027]; a current sense portion configured to sense a signal based on the second switch (Fig. 1 shows zero-crossing amplifier U2 i.e. current sense portion which is arranged to detect voltage difference across the drain and the source terminals of M2 i.e. a signal based on second switch said voltage signal having a magnitude corresponding to the magnitude of the current flow) [0031, 0045]; and an accumulating portion (Fig. 1 shows U3, U4 and C2 comprising accumulating portion) including the capacitor (Fig. 1 shows capacitor C2) and configured to accumulate information according to the signal based on the on-resistance of the second switch (accumulate information according to the signal based on the on-resistance of the second switch) [0024, 0044], wherein the controller controls off timing of the first switch based on a first voltage (Fig. 1 shows PWM control logic i.e. controller controls off timing of the first switch M1 based on a first voltage) [0027], a feedback voltage corresponding to an output voltage of the switching power supply device (Fig. 1 shows FB i.e. feedback voltage corresponding to an output voltage of the SMPS 100) [0029], and a reference voltage (Fig. 1 shows Vref from U8) [0029], the first voltage being a voltage reflecting the information accumulated by the accumulating portion (first voltage being a voltage reflecting the information accumulated by the accumulating portion comprising U3, U4, C2) [0025, 0027-0029, 0031-32, 0045, 0061]. However, Liu does not explicitly teach: current sense based on an on-resistance of the second switch; and a charging switch configured to be connected to the current sense portion and configured to, when the second switch is an on state, control charging of a capacitor according to the signal based on the on-resistance of the second switch; capacitor configured to connect to the charging switch. However, Ouyang teaches: current sense based on an on-resistance of the second switch (zero crossing detector 133 is configured to detect current Im2 via testing drain to source voltage Vds based on an on-resistance) [0026]; and a charging switch (Fig. 2 shows switch S1) configured to be connected to the current sense portion (Fig. 2 shows switch S1 being electrically connected to zero crossing detector 133 i.e. current sense portion) and configured to, when the second switch is an on state (when Q1 is ineffective, M1 i.e. first switch is OFF and M2 i.e. second switch is ON and switch S1 is ON) [0042], control charging of a capacitor according to the signal based on the on-resistance of the second switch (when second switch M2 is ON, S1 is ON and controls charging of a capacitor CO by outputting output voltage Vo accordingly) [0033, 0038, 0042]; capacitor configured to connect to the charging switch (Fig. 2 shows capacitor Co electrically connected to charging switch S1). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have current sensed based on an on-resistance of the second switch in order to sense the current without additional circuitry thereby ensuring efficient use of space in the circuit; and a charging switch configured to be connected to the current sense portion and configured to, when the second switch is an on state, control charging of a capacitor according to the signal based on the on-resistance of the second switch and capacitor configured to connect to the charging switch as taught by Ouyang in order to protect the circuitry current spikes. Regarding claim 2, Liu teaches wherein the controller includes an error amplifier configured to amplify a difference voltage between the feedback voltage and the reference voltage (Fig. 1 shows error amplifier U7 to amplify a difference voltage between feedback voltage FB and reference voltage Vref) [0029]. Regarding claim 3, Liu teaches wherein the controller includes: a comparator configured to compare the first voltage with the output voltage of the error amplifier so as to generate a reset signal as a comparison signal (Fig. 1 shows comparator U5 to compare first voltage with the output voltage of the error amplifier U7 so as to generate a reset signal as a comparison signal) [0029, 0032]; an oscillator configured to generate a set signal as a clock signal of a predetermined frequency (Fig. 1 shows oscillator U6 configured to generate a set signal as a clock signal CLK of a predetermined frequency) [0026, 0029, 0033]; and a timing control circuit configured to control on and off states of the first switch and on and off states of the second switch in accordance with the set signal and the reset signal (Fig. 1 shows current estimation logic U4 which intakes CLK signal thereby configured to control On and Off of M1 and M2 via outputting to U3 in according with set and reset signal as U4 receives the set signal from OSC) [0029, 0031-33]. Regarding claim 4, Liu teaches wherein the controller controls the first switch and the second switch in accordance with the current sensed by the current sensing portion (Fig. 1 shows switching controller 100 controls M1 and M2 in accordance with the current sensed by ZCA U2 i.e. current sensing portion) [0029, 0031-032]. Regarding claim 5, Liu teaches wherein the second switch is a MOS transistor (Fig. 1 shows switch M2 to be a MOSFET) [0023], and the current sensing portion senses the current flowing in the second switch by using a voltage between both ends of an on resistor of the MOS transistor (Fig. 1 shows ZCA U2 i.e. current sensing portion senses the current flowing in M2 by using a voltage between both ends of the MOFET) [0024, 0031]. Regarding claim 6, , Liu teaches a switching power supply device (Fig. 1 shows switching power supply device) [0024] comprising: a controller (Fig. 1 shows switching controller comprising switching control device U3) configured to generate a first gate signal and a second gate signal (Fig. 1 shows switching control device U3 configured to generate a first switching control signal and a second switching control signal) [0028] to control a first switch to which an input voltage is applied (Fig. 1 shows first switch M1 is controlled by switching control signal from U3 to receive an input voltage Vin) [0024-25] and a second switch connected to the first switch (Fig. 1 shows second switch M2 electrically connected to first switch M1) [0027]; a current sense portion configured to sense a signal based on the second switch (Fig. 1 shows zero-crossing amplifier U2 i.e. current sense portion which is arranged to detect voltage difference across the drain and the source terminals of M2 i.e. a signal based on second switch said voltage signal having a magnitude corresponding to the magnitude of the current flow) [0031, 0045]; and an accumulating portion (Fig. 1 shows U3, U4 and C2 comprising accumulating portion) configured to accumulate information according to the signal based on the on-resistance of the second switch (accumulate information according to the signal based on the on-resistance of the second switch) [0024, 0044], wherein the controller controls off timing of the first switch based on a first voltage (Fig. 1 shows PWM control logic i.e. controller controls off timing of the first switch M1 based on a first voltage) [0027], a feedback voltage corresponding to an output voltage of the switching power supply device (Fig. 1 shows FB i.e. feedback voltage corresponding to an output voltage of the SMPS 100) [0029], and a reference voltage (Fig. 1 shows Vref from U8) [0029], the first voltage being based on the current flowing in the second switch when the first switch is an off state and the second switch is an on state (first voltage being based on the current flowing in the M2 when the M1 is off and M2 is on) [0025, 0027-0029, 0031-32, 0045, 0061]. However, Liu does not explicitly teach: current sense based on an on-resistance of the second switch; and a charging switch configured to be connected to the current sense portion and configured to, when the second switch is on, control charging of a capacitor according to the signal based on the on-resistance of the second switch; capacitor configured to connect to the charging switch. However, Ouyang teaches: current sense based on an on-resistance of the second switch (zero crossing detector 133 is configured to detect current Im2 via testing drain to source voltage Vds based on an on-resistance) [0026]; and a charging switch (Fig. 2 shows switch S1) configured to be connected to the current sense portion (Fig. 2 shows switch S1 being electrically connected to zero crossing detector 133 i.e. current sense portion) and configured to, when the second switch is on (when Q1 is ineffective, M1 i.e. first switch is OFF and M2 i.e. second switch is ON and switch S1 is ON) [0042], control charging of a capacitor according to the signal based on the on-resistance of the second switch (when second switch M2 is ON, S1 is ON and controls charging of a capacitor CO by outputting output voltage Vo accordingly) [0033, 0038, 0042]; capacitor configured to connect to the charging switch (Fig. 2 shows capacitor Co electrically connected to charging switch S1). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have current sensed based on an on-resistance of the second switch in order to sense the current without additional circuitry thereby ensuring efficient use of space in the circuit; and a charging switch configured to be connected to the current sense portion and configured to, when the second switch is an on state, control charging of a capacitor according to the signal based on the on-resistance of the second switch and capacitor configured to connect to the charging switch as taught by Ouyang in order to protect the circuitry current spikes. Regarding claim 7, Liu teaches wherein the controller includes an error amplifier configured to amplify a difference voltage between the feedback voltage and the reference voltage (Fig. 1 shows error amplifier U7 to amplify a difference voltage between feedback voltage FB and reference voltage Vref) [0029]. Regarding claim 8, Liu teaches wherein the controller includes: a comparator configured to compare the first voltage with the output voltage of the error amplifier so as to generate a reset signal as a comparison signal (Fig. 1 shows comparator U5 to compare first voltage with the output voltage of the error amplifier U7 so as to generate a reset signal as a comparison signal) [0029, 0032]; an oscillator configured to generate a set signal as a clock signal of a predetermined frequency (Fig. 1 shows oscillator U6 configured to generate a set signal as a clock signal CLK of a predetermined frequency) [0026, 0029, 0033]; and a timing control circuit configured to control on and off states of the first switch and on and off states of the second switch in accordance with the set signal and the reset signal (Fig. 1 shows current estimation logic U4 which intakes CLK signal thereby configured to control On and Off of M1 and M2 via outputting to U3 in according with set and reset signal as U4 receives the set signal from OSC) [0029, 0031-33]. Regarding claim 9, Liu teaches wherein the controller controls the first switch and the second switch in accordance with the current sensed by the current sensing portion (Fig. 1 shows switching controller 100 controls M1 and M2 in accordance with the current sensed by ZCA U2 i.e. current sensing portion) [0029, 0031-032]. Regarding claim 10, Liu teaches wherein the second switch is a MOS transistor (Fig. 1 shows switch M2 to be a MOSFET) [0023], and the current sensing portion senses the current flowing in the second switch by using a voltage between both ends of an on resistor of the MOS transistor (Fig. 1 shows ZCA U2 i.e. current sensing portion senses the current flowing in M2 by using a voltage between both ends of the MOFET) [0024, 0031]. Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0336857 (Liu) in view of US 2014/0160601 (Ouyang) further in view of US 2012/0181931 (Katsura). Regarding claim 11, Liu and Ouyang do not teach in-vehicle equipment comprising the switching power supply device according to claim 1. However, Katsura teaches in-vehicle equipment comprising the switching power supply device according to claim 1 [0076, 0080]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have in-vehicle equipment comprising the switching power supply device according to claim 1 as taught by Katsura in order to supply constant and efficient power to the in-vehicle equipment of a vehicle. Regarding claim 12, Liu and Ouyang do not teach a vehicle comprising: the in-vehicle equipment according to claim 11; and a battery configured to supply electric power to the in-vehicle equipment. However, Katsura teaches a vehicle comprising: the in-vehicle equipment according to claim 11; and a battery configured to supply electric power to the in-vehicle equipment [0076, 0080]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have a vehicle comprising: the in-vehicle equipment according to claim 11; and a battery configured to supply electric power to the in-vehicle equipment as taught by Katsura in order to supply constant and efficient power to the in-vehicle equipment of a vehicle. Regarding claim 13, Liu and Ouyang do not teach in-vehicle equipment comprising the switching power supply device according to claim 6. However, Katsura teaches in-vehicle equipment comprising the switching power supply device according to claim 6 [0076, 0080]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have in-vehicle equipment comprising the switching power supply device according to claim 6 as taught by Katsura in order to supply constant and efficient power to the in-vehicle equipment of a vehicle. Regarding claim 14, Liu and Ouyang do not teach a vehicle comprising: the in-vehicle equipment according to claim 13; and a battery configured to supply electric power to the in-vehicle equipment. However, Katsura teaches a vehicle comprising: the in-vehicle equipment according to claim 13; and a battery configured to supply electric power to the in-vehicle equipment [0076, 0080]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have a vehicle comprising: the in-vehicle equipment according to claim 13; and a battery configured to supply electric power to the in-vehicle equipment as taught by Katsura in order to supply constant and efficient power to the in-vehicle equipment of a vehicle. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SWARNA N CHOWDHURI whose telephone number is (571)431-0696. The examiner can normally be reached Mon-Fri 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at 571-272-7496. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. SWARNA N. CHOWDHURI Examiner Art Unit 2836 /S.N.C/Examiner, Art Unit 2836 /DANIEL CAVALLARI/Primary Examiner, Art Unit 2836
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Prosecution Timeline

Dec 23, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §103, §DP (current)

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
98%
With Interview (+21.9%)
3y 1m
Median Time to Grant
Low
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