Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Acknowledgement is made of remarks filed 23 December 2025 in which no claims were amended. Claims 1-9 are currently pending and an office action on the merits follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pub. No. 2019/0043430 by Jung (“Jung”).
As to claim 1, Jung discloses a display driving device (Jung, organic light-emitting display device 1, Figure 5), applicable for at least one display area, comprising:
a plurality of drivers (Jung, plurality of diving ICs 202, Figure 6) configured to drive a plurality of pixels in the at least one display area (Jung, The display panel part 200 includes a display panel in which a plurality of data lines, a plurality of gate lines and a plurality of sub-pixels are arranged. A data driver 201 to which a plurality of driving ICs 202 is connected is arranged on the left (L) and Right (R) of the panel in order to drive the data lines. Figure 6, ¶ [0065]), respectively;
at least one timing controller (Jung, timing control circuit 100, Figure 6) configured to obtain a first addressed display signal of the plurality of pixels and generate a second addressed display signal based on the first addressed display signal (Jung, Referring to FIG. 6, a timing control circuit 100 provides power or video data and control data to a display panel part 200 using a plurality of flexible flat cables (FFC) 300. In addition, the timing control circuit 100 receives sensing data of sub-pixels from the display panel part 200 for display compensation. Figure 6, ¶ [0064])(Jung, a NAND type flash memory 110 can be connected to the timing control circuit 100. This is for the purpose of storing data necessary for operation of the timing control circuit 100, Figure 6, ¶ [0068])(Jung, The converter 210 can receive sensing data of sub-pixels, provided through the data driver 201 of the panel part 200, and/or temperature sensing data provided from a temperature sensor included in the panel part. The received sensing data and temperature sensing data are transmitted to the timing control circuit 100 and used as sensing information for generating a compensation control signal of the timing control circuit 100. Figures 6 and 7, ¶ [0070]); Jung teaches the timing control circuit 100 transmitting display signals to the display panel part 200 and receiving signals from the display panel part 200 to compensate the transmitted display signals.
at least one intermediate controller (Jung, display panel part 200 with left and right data drivers 201, Figure 6) connected to the at least one timing controller (Jung, timing control circuit 100, Figure 6), and configured to transmit at least one portion of the second addressed display signal to the plurality of drivers (Jung, plurality of diving ICs 202, Figure 6) according to a plurality of address information within the second addressed display signal to drive the at least one display area (Jung, The display panel part 200 includes a display panel in which a plurality of data lines, a plurality of gate lines and a plurality of sub-pixels are arranged. A data driver 201 to which a plurality of driving ICs 202 is connected is arranged on the left (L) and Right (R) of the panel in order to drive the data lines. Figure 6, ¶ [0065]);
wherein the at least one intermediate controller has lower signal processing capability than the at least one timing controller (Jung, Referring to FIG. 6, a timing control circuit 100 provides power or video data and control data to a display panel part 200 using a plurality of flexible flat cables (FFC) 300. In addition, the timing control circuit 100 receives sensing data of sub-pixels from the display panel part 200 for display compensation. Figure 6, ¶ [0064])(Jung, The data driver 201 includes a first memory 220 for storing data including display panel compensation data, and a converter 210 which performs communication with the timing control circuit 100 through a long-distance signal transmission system, converts a signal provided from the timing control circuit and transmits the converted signal to the first memory 220, converts a signal provided from the first memory 220 and transmits the converted signal to the timing control circuit 100. Figure 6, ¶ [0066]). As described by Jung, the timing control circuit 100 performs compensation and the display panel part 200 merely includes a converter, memory, and display driving ICs for providing the compensated image data from the timing controller to the data lines. Thus, the display panel part 200 has lower signal processing capability as it can not compensate the image data like the timing control circuit 100.
As to claim 2, Jung discloses the display driving device wherein the at least one intermediate controller (Jung, display panel part 200 with left and right data drivers 201, Figure 6) comprises:
a signal input port connected to the at least one timing controller (Jung, timing control circuit 100, Figure 6), configured to receive the second addressed display signal (Jung, Referring to FIG. 6, a timing control circuit 100 provides power or video data and control data to a display panel part 200 using a plurality of flexible flat cables (FFC) 300. Figure 6, ¶ [0064]);
a plurality of signal output ports (Jung, Referring to FIG. 6, a timing control circuit 100 provides power or video data and control data to a display panel part 200 using a plurality of flexible flat cables (FFC) 300. Figure 6, ¶ [0064]);
a decoder (Jung, decoder 213 which in inside the converter 210, Figure 7) connected to the signal input port and configured to generate a third addressed display signal based on the plurality of address information and the second addressed display signal (Jung, a decoder 213 for decoding data according to a control signal of the memory control circuit 21, Figure 7, ¶ [0069]); and
a serial-to-parallel converter (Jung, deserializer 215 which is inside the converter 210, Figure 7) connected to the decoder and to at least one portion of the plurality of signal output ports, configured to convert the third addressed display signal into a plurality of parallel signals (Jung, a deserializer 215 for converting serial electric signals received from the timing control circuit 100 through a long-distance signal transmission system into parallel electric signals. Figure 7, ¶ [0069]), and outputting the plurality of parallel signals to the plurality of drivers through the at least one portion of the plurality of signal output ports (Jung, The display panel part 200 includes a display panel in which a plurality of data lines, a plurality of gate lines and a plurality of sub-pixels are arranged. A data driver 201 to which a plurality of driving ICs 202 is connected is arranged on the left (L) and Right (R) of the panel in order to drive the data lines. Figure 6, ¶ [0065]).
As to claim 3, Jung discloses the display driving device wherein the signal input port and the plurality of signal output ports use a low-voltage differential signaling technology (Jung, Referring to FIG. 6, a timing control circuit 100 provides power or video data and control data to a display panel part 200 using a plurality of flexible flat cables (FFC) 300. Figure 6, ¶ [0064]). As shown in figure 6 of Jung, the flexible flat cables FFC utilize LVDS (low-voltage differential signaling).
As to claim 4, Jung discloses the display driving device wherein a quantity of the at least one intermediate controller is plural (Jung, display panel part 200 includes a left and right data drivers 201. Figure 6), and the plurality of signal output ports of one of the intermediate controllers comprises:
a first output port connected to the signal input port and to the signal input port of another one of the intermediate controllers(Jung, Referring to FIG. 6, a timing control circuit 100 provides power or video data and control data to a display panel part 200 using a plurality of flexible flat cables (FFC) 300. Figure 6, ¶ [0064]); and
a plurality of second output ports connected to the serial-to-parallel converter (Jung, a deserializer 215 for converting serial electric signals received from the timing control circuit 100 through a long-distance signal transmission system into parallel electric signals. Figure 7, ¶ [0069]), and connected to the plurality of drivers, respectively (Jung, The display panel part 200 includes a display panel in which a plurality of data lines, a plurality of gate lines and a plurality of sub-pixels are arranged. A data driver 201 to which a plurality of driving ICs 202 is connected is arranged on the left (L) and Right (R) of the panel in order to drive the data lines. Figure 6, ¶ [0065]) (Jung, Referring to FIG. 6, a timing control circuit 100 provides power or video data and control data to a display panel part 200 using a plurality of flexible flat cables (FFC) 300. Figure 6, ¶ [0064]).
As to claim 5, Jung discloses the display driving device wherein a quantity of the at least one intermediate controller is plural (Jung, display panel part 200 includes a left and right data drivers 201. Figure 6), and a signal output port of a first intermediate controller of the at least one intermediate controller is connected to a signal input port of a second intermediate controller of the at least one intermediate controller, and the first intermediate controller is configured to transmit the at least one portion of the second addressed display signal to the second intermediate controller (Jung, a NAND type flash memory is used as the first memory 220. NAND type flash memories (for example, NAND1 and NAND2) can be respectively arranged in the left data driver L and the right data driver R. Figure 6, ¶ [0067]). As shown in figure 6 of Jung, the NAND2 memory is connected to the left and right data drivers 201.
As to claim 6, Jung discloses the display driving device wherein each of the plurality of drivers is configured to extract a target portion of the at least one portion of the second addressed display signal based on part of the plurality of address information within the at least one portion of the second addressed display signal, and drive the at least one display area based on the target portion (Jung, The display panel part 200 includes a display panel in which a plurality of data lines, a plurality of gate lines and a plurality of sub-pixels are arranged. A data driver 201 to which a plurality of driving ICs 202 is connected is arranged on the left (L) and Right (R) of the panel in order to drive the data lines. Figure 6, ¶ [0065]). Jung teaches the plurality of driving ICs 202 which drive specific data lines, which are portions of the display panel.
As to claim 7, Jung discloses the display driving device wherein the at least one intermediate controller (Jung, display panel part 200 with left and right data drivers 201, Figure 6) is configured to divide the at least one portion of the second addressed display signal into a plurality of sub-signals based on the plurality of address information and to transmit the plurality of sub-signals to the plurality of drivers, respectively (Jung, The display panel part 200 includes a display panel in which a plurality of data lines, a plurality of gate lines and a plurality of sub-pixels are arranged. A data driver 201 to which a plurality of driving ICs 202 is connected is arranged on the left (L) and Right (R) of the panel in order to drive the data lines. Figure 6, ¶ [0065]). As shown in figure 6 of Jung, the display driving is divided into a left and right data drivers 201.
As to claim 8, Jung discloses the display driving device wherein the at least one intermediate controller does not perform image enhancement and compensation (Jung, The data driver 201 includes a first memory 220 for storing data including display panel compensation data, and a converter 210 which performs communication with the timing control circuit 100 through a long-distance signal transmission system, converts a signal provided from the timing control circuit and transmits the converted signal to the first memory 220, converts a signal provided from the first memory 220 and transmits the converted signal to the timing control circuit 100. Figure 6, ¶ [0066]). As described by Jung, the timing control circuit 100 performs compensation and the display panel part 200 merely includes a converter, memory, and display driving ICs for providing the compensated image data from the timing controller to the data lines. Thus, the display panel part 200 does not perform image enhancement and compensation.
As to claim 9, Jung discloses a display (Jung, organic light-emitting display device 1, Figure 5), comprising:
the display driving device according to claim 1 (Jung, organic light-emitting display device 1, Figure 5); and
the at least one display area connected to and controlled by the display driving device (Jung, The display panel part 200 includes a display panel in which a plurality of data lines, a plurality of gate lines and a plurality of sub-pixels are arranged. A data driver 201 to which a plurality of driving ICs 202 is connected is arranged on the left (L) and Right (R) of the panel in order to drive the data lines. Figure 6, ¶ [0065]).
Response to Arguments
Applicant's arguments filed 23 December 2025 have been fully considered but they are not persuasive.
Applicant’s representative asserts in pages 5 and 6 of remarks, the cited prior art of Jung does not teach the intermediate controller having functionality recited in claim 1. Specifically, Jung does not teach any functionality of: parsing address information with a display signal, generating addressed sub-signals, or distributing addressed signal portions to multiple drivers.
The Office respectfully disagrees with this assertion as the display panel part 200 includes data drivers 201 which then drive data lines. Thus, the display panel part is “distributing addressed signal portions to multiple drivers” in order to produce images in the display area.
Applicant’s representative asserts in page 6 of remarks, Jung does not teach the “second addressed display signal” as recited in claim 1.
The Office respectfully disagrees with this assertion as Jung teaches, as shown in the rejection above, the timing control circuit 100 uses sensing information to generate a compensated display signal (second addressed display signal). Thus, Jung teaches the cited limitation.
Applicant’s representative asserts in pages 6 and 7 of remarks, Jung does not teach any component that transmits display data based on address information.
The Office respectfully disagrees with this assertion as Jung teaches, as shown in the rejection above, the display panel part 200 contains multiple driving ICs 202 which are connected to specific data lines. Thus, the display panel part transmits a portion of the display signal to the driving ICs.
Applicant’s representative asserts in page 7 of remarks, Jung does not teach a component having lower signal processing capability than a timing controller.
The Office respectfully disagrees with this assertion as the display panel part 200 with the left and right data drivers 201 have lower signal processing capability than the timing controller. As described in the rejection, the timing control circuit performs processing and generating of compensated image data, whereas the display panel part and data drivers does not include those capabilities. Thus, Jung teaches the display panel part having lower signal processing capability than a timing controller as claimed.
Applicant’s representative asserts in pages 7 and 8 of remarks, examiner does not acknowledge the architectural purpose of the claimed system, that is, reducing the number of timing controllers by introducing an intermediate control performing address-based data routing.
The Office respectfully disagrees with this assertion as the claims do not include any discussion of this architecture. Thus, as this is not claimed, these remarks are not persuasive.
Applicant’s representative asserts in page 8 of remarks, the claims are allowable and a notice of allowance should be sent.
The Office respectfully disagrees with this assertion and submits the rejection and response above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Pub. No. 2019/0156728 by Yu et al. teaches a display device and timing controller which produces additional display data for specific pixels.
U.S. Patent No. 11,176,906 by Aubineau et al. teaches a display device with a video generation circuit which transmits data via an LDVS to a display circuit.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623