DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bradshaw et al. (US 2020/0081829).
In regards to claim 1, Bradshaw teaches a memory device, comprising:
one or more components configured to:
receive, from a host device, a write command instructing the memory device to write host data to a portion of a memory (“The wear-leveling process can be triggered by a need to service a write request from a host system 120 or similar event.”, paragraph 0034) associated with a logical address (“address translations between a logical block address and a physical block address that are associated with the memory components 112A to 112N”, paragraph 0026);
determine a physical location of the memory associated with the logical address (“address translations between a logical block address and a physical block address that are associated with the memory components 112A to 112N”, paragraph 0026) by using a wear leveling algorithm to map the logical address to the physical location of the memory (“The wear-leveling remapper 113 assigns the destination chunk to a location in the usable logical address space of the memory subsystem 110 (Block 205). The destination selected by the wear-leveling remapper 113 can be the location that is currently held by the source chunk. In this manner, the wear-leveling remapper 113 swaps the source chunk with the destination chunk in the logical address space of the memory subsystem 110. The wear-leveling remapper 113 can update a virtualization table or similar mechanism for creating and maintaining a virtualized representation of the memory subsystem 110.”, paragraph 0036),
wherein the wear leveling algorithm is based on a randomized parameter and the randomized parameter is a time threshold (“In other embodiments, the wear-leveling process can include policies for triggering operation based on random or fixed times.”, paragraph 0054), and
wherein the wear leveling algorithm is associated with a periodic wear leveling scheme and the periodic wear leveling scheme is associated with a wear leveling step event performed after the time threshold is satisfied (“An example trigger can be a function of any number of inputs, including writes and/or reads to the segment, writes and/or reads to cells adjacent to cells in the segment, spatial locality of block accesses within the segment, available but unused read/write bandwidth, periodic triggering, and random time delta triggering.”, paragraph 0080), the wear leveling step event comprising determining the physical location of the memory (“Similarly, the wear-leveling process can update the physical address space information for a logical address space entry of the source chunk to be the physical address space information of the destination chunk.”, paragraph 0057); and
write the host data to the physical location of the memory (“In a case where there is valid data in the source chunk, then the wear-leveling process performs a phase driven migration of the valid data in the source chunk to the destination chunk (Block 507). The phase driven migration can include the generation of a copy of the current virtualization table and generation of the desired virtualization table, the copying of the valid data to the destination chunk, and the update of the current virtualization table to match the desired virtualization table as each chunk is copied.”, paragraph 0058).
In regards to claim 10, Bradshaw teaches a method, comprising:
receiving, by a memory device and from a host device, a write command instructing the memory device to write host data to a portion of a memory (“The wear-leveling process can be triggered by a need to service a write request from a host system 120 or similar event.”, paragraph 0034) associated with a logical address (“address translations between a logical block address and a physical block address that are associated with the memory components 112A to 112N”, paragraph 0026);
determining, by the memory device, a physical location of the memory associated with the logical address (“address translations between a logical block address and a physical block address that are associated with the memory components 112A to 112N”, paragraph 0026) by using a wear leveling algorithm to map the logical address to the physical location of the memory (“The wear-leveling remapper 113 assigns the destination chunk to a location in the usable logical address space of the memory subsystem 110 (Block 205). The destination selected by the wear-leveling remapper 113 can be the location that is currently held by the source chunk. In this manner, the wear-leveling remapper 113 swaps the source chunk with the destination chunk in the logical address space of the memory subsystem 110. The wear-leveling remapper 113 can update a virtualization table or similar mechanism for creating and maintaining a virtualized representation of the memory subsystem 110.”, paragraph 0036),
wherein the portion of the memory is associated with a wear leveling pool (“If there is more than one possible destination chunk, the wear-leveling remapper 113 can select one chunk from the set of chunks in the unusable address space of the memory subsystem 110.”, paragraph 0035), and
wherein the wear leveling algorithm maps the logical address to a portion of the wear leveling pool based on a randomized parameter and the randomized parameter is a time threshold (id.; “In other embodiments, the wear-leveling process can include policies for triggering operation based on random or fixed times.”, paragraph 0054), and
wherein the wear leveling algorithm is associated with a periodic wear leveling scheme and the periodic wear leveling scheme is associated with a wear leveling step event performed after the time threshold is satisfied (“An example trigger can be a function of any number of inputs, including writes and/or reads to the segment, writes and/or reads to cells adjacent to cells in the segment, spatial locality of block accesses within the segment, available but unused read/write bandwidth, periodic triggering, and random time delta triggering.”, paragraph 0080), the wear leveling step event comprising determining the physical location of the memory (“Similarly, the wear-leveling process can update the physical address space information for a logical address space entry of the source chunk to be the physical address space information of the destination chunk.”, paragraph 0057); and
writing, by the memory device, the host data to the physical location of the memory (“In a case where there is valid data in the source chunk, then the wear-leveling process performs a phase driven migration of the valid data in the source chunk to the destination chunk (Block 507). The phase driven migration can include the generation of a copy of the current virtualization table and generation of the desired virtualization table, the copying of the valid data to the destination chunk, and the update of the current virtualization table to match the desired virtualization table as each chunk is copied.”, paragraph 0058).
In regards to claim 19, Bradshaw teaches a non-transitory computer-readable medium storing a set of instructions (“The data storage system 1218 can include a machine-readable storage medium 1224 (also known as a computer-readable medium) on which is stored one or more sets of instructions 1226 or software embodying any one or more of the methodologies or functions described herein.”, paragraph 0089), the set of instructions comprising:
one or more instructions that, when executed by one or more processors of a memory device, cause the memory device (“The processing device 1202 is configured to execute instructions 1226 for performing the operations and steps discussed herein.”, paragraph 0088) to:
receive, from a host device, a write command instructing the memory device to write host data to a portion of a memory (“The wear-leveling process can be triggered by a need to service a write request from a host system 120 or similar event.”, paragraph 0034) associated with a logical address (“address translations between a logical block address and a physical block address that are associated with the memory components 112A to 112N”, paragraph 0026);
determine a physical location of the memory associated with the logical address (“address translations between a logical block address and a physical block address that are associated with the memory components 112A to 112N”, paragraph 0026) by using a wear leveling algorithm to map the logical address to the physical location of the memory (“The wear-leveling remapper 113 assigns the destination chunk to a location in the usable logical address space of the memory subsystem 110 (Block 205). The destination selected by the wear-leveling remapper 113 can be the location that is currently held by the source chunk. In this manner, the wear-leveling remapper 113 swaps the source chunk with the destination chunk in the logical address space of the memory subsystem 110. The wear-leveling remapper 113 can update a virtualization table or similar mechanism for creating and maintaining a virtualized representation of the memory subsystem 110.”, paragraph 0036),
wherein the wear leveling algorithm is associated with a periodic wear leveling scheme based on a time threshold, the periodic wear leveling scheme associated with a wear leveling step event performed after the time threshold is satisfied (“An example trigger can be a function of any number of inputs, including writes and/or reads to the segment, writes and/or reads to cells adjacent to cells in the segment, spatial locality of block accesses within the segment, available but unused read/write bandwidth, periodic triggering, and random time delta triggering.”, paragraph 0080), the wear leveling step event comprising determining the physical location of the memory (“Similarly, the wear-leveling process can update the physical address space information for a logical address space entry of the source chunk to be the physical address space information of the destination chunk.”, paragraph 0057), and
wherein the wear leveling algorithm randomizes the time threshold (“In other embodiments, the wear-leveling process can include policies for triggering operation based on random or fixed times.”, paragraph 0054); and
write the host data to the physical location of the memory (“In a case where there is valid data in the source chunk, then the wear-leveling process performs a phase driven migration of the valid data in the source chunk to the destination chunk (Block 507). The phase driven migration can include the generation of a copy of the current virtualization table and generation of the desired virtualization table, the copying of the valid data to the destination chunk, and the update of the current virtualization table to match the desired virtualization table as each chunk is copied.”, paragraph 0058).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7, 13-16, and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Bradshaw et al. (US 2020/0081829) in view of Helmick et al. (US 2020/0105354).
In regards to claims 4 and 13, Bradshaw further teaches that the wear leveling algorithm is associated with multiple wear leveling step events (“The wear-leveling process can be continuous and repeating.”, paragraph 0048) and multiple instances of the randomized parameter, with each wear leveling step event, of the multiple wear leveling step events, being associated with a corresponding instance of the randomized parameter, of the multiple instances of the randomized parameter (“In other embodiments, the wear-leveling process can include policies for triggering operation based on random or fixed times.”, paragraph 0054).
Bradshaw fails to teach that the multiple instances of the randomized parameter are symmetrically distributed about a mean value of the multiple instances of the randomized parameter. Helmick teaches that the multiple instances of the randomized parameter are symmetrically distributed about a mean value of the multiple instances of the randomized parameter (“In further embodiments, a map component 150 may change a wear-leveling parameter to a value randomly or pseudo-randomly generated according to a probability distribution, such as a uniform probability distribution, a normal distribution, a Bernoulli distribution, a binomial distribution, or the like, where the probability distribution may be constrained to values suitable for the parameter.”, paragraph 0119) in order to obtain suitably constrained random parameters (id.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bradshaw with Helmick such that the multiple instances of the randomized parameter are symmetrically distributed about a mean value of the multiple instances of the randomized parameter in order to obtain suitably constrained random parameters (id.).
In regards to claim 20, Bradshaw further teaches that the wear leveling algorithm is associated with multiple wear leveling step events (“The wear-leveling process can be continuous and repeating.”, paragraph 0048) and multiple instances of the time threshold, with each wear leveling step event, of the multiple wear leveling step events, being associated with a corresponding instance of the time threshold, of the multiple instances of the time threshold (“In other embodiments, the wear-leveling process can include policies for triggering operation based on random or fixed times.”, paragraph 0054).
Bradshaw fails to teach that the multiple instances of the one of the time threshold or the activity threshold are symmetrically distributed about a mean value of the multiple instances of the one of the time threshold or the activity threshold. Helmick teaches that the multiple instances of the one of the time threshold or the activity threshold are symmetrically distributed about a mean value of the multiple instances of the one of the time threshold or the activity threshold (“In further embodiments, a map component 150 may change a wear-leveling parameter to a value randomly or pseudo-randomly generated according to a probability distribution, such as a uniform probability distribution, a normal distribution, a Bernoulli distribution, a binomial distribution, or the like, where the probability distribution may be constrained to values suitable for the parameter.”, paragraph 0119) in order to obtain suitably constrained random parameters (id.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bradshaw with Helmick such that the multiple instances of the one of the time threshold or the activity threshold are symmetrically distributed about a mean value of the multiple instances of the one of the time threshold or the activity threshold in order to obtain suitably constrained random parameters (id.).
In regards to claims 5, 14, and 21, Helmick further teaches that the multiple instances of the randomized parameter are symmetrically distributed about the mean value of the multiple instances of the randomized parameter based on one of:
a uniform distribution (“a uniform probability distribution”, paragraph 0119),
a triangular distribution,
an anti-triangular distribution, or
a Gaussian distribution (“a normal distribution”, paragraph 0119).
In regards to claims 6, 15, and 22, Bradshaw further teaches that the wear leveling algorithm is associated with multiple wear leveling step events (“The wear-leveling process can be continuous and repeating.”, paragraph 0048), and
wherein the one or more instructions further comprise instructions that, when executed by the one or more processors of the memory device, cause the memory device to determine whether to move from a first wear leveling step event, of the multiple wear leveling step events, to a second wear leveling step event, of the multiple wear leveling step events, by comparing a counter to the parameter/time threshold (“If the objective of the wear-leveling is to wear-level write operations over the available chunks, then the wear-leveling process can include a policy to trigger based on a threshold count of the number of writes to any or all chunks in the memory subsystem 110—(e.g., any of the dice in the example topology).”, paragraph 0053).
Bradshaw fails to teach that the time threshold is a randomized parameter/time threshold. Helmick teaches that the time threshold is a randomized parameter/time threshold (“For example, in one embodiment, a map component 150 may randomly or pseudo-randomly select a number of writes until the next mapping, as a trigger 702, from a range of 50-150 writes.”, paragraph 0118) which “may further frustrate wear-based attacks” (paragraph 0034). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bradshaw with Helmick such that the time threshold is a randomized parameter/time threshold which “may further frustrate wear-based attacks” (id.).
In regards to claims 7, 16, and 23, Bradshaw further teaches that the counter is associated with one of a quantity of clock cycles associated with a wear leveling step event, of the multiple wear leveling step events, or a quantity of accesses to the portion of the memory associated with the wear leveling step event (“If the objective of the wear-leveling is to wear-level write operations over the available chunks, then the wear-leveling process can include a policy to trigger based on a threshold count of the number of writes to any or all chunks in the memory subsystem 110—(e.g., any of the dice in the example topology).”, paragraph 0053).
Claims 8, 17, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Bradshaw et al. (US 2020/0081829) in view of Kannan et al. (US 2021/0334157).
In regards to claims 8, 17, and 24, Bradshaw teaches claims 1, 10, and 19. Bradshaw fails to teach that the one or more components are further configured to determine the randomized parameter by using a pseudo-random vector generator that is based on an identifier associated with the memory device. Kannan teaches that the one or more components are further configured to determine the randomized parameter by using a pseudo-random vector generator that is based on an identifier associated with the memory device (“One embodiment of the ordering mixer 404 could use a pseudorandom generator 450, for example with an ID used as a seed for determinism, reproducibility and reversibility of a pseudorandom number sequence. For example, the ID could be an identifier of the RAID stripe, an identifier of a storage node or storage unit, an identifier of a solid-state memory component, or other identifier that can be used for the write data and reused for the read data.”, paragraph 0213) “for determinism, reproducibility and reversibility of a pseudorandom number sequence” (id.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bradshaw with Kannan such that the one or more components are further configured to determine the randomized parameter by using a pseudo-random vector generator that is based on an identifier associated with the memory device “for determinism, reproducibility and reversibility of a pseudorandom number sequence” (id.).
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bradshaw et al. (US 2020/0081829) in view of Kannan et al. (US 2021/0334157) and Grifski (“How to Generate Any Random Number From a Zero to One Range”).
In regards to claims 9 and 18, Bradshaw in view of Kannan teaches claims 8 and 17. Bradshaw in view of Kannan fails to teach that the one or more components, to determine the randomized parameter by using the pseudo-random vector generator, are configured to determine the randomized parameter based on adding a value generated by the pseudo-random vector generator to a minimum value associated with the randomized parameter. Grifski teaches that the one or more components, to determine the randomized parameter by using the pseudo-random vector generator, are configured to determine the randomized parameter based on adding a value generated by the pseudo-random vector generator to a minimum value associated with the randomized parameter (“As far as the shifting factor, we only need to calculate the difference between lower bound and 0, which is always the lower bound. In this case, our shifting factor is 150. Put it all together and we have the following equation: random_in_range = random_initial * 100 + 150”, page 5) in order to take advantage of an existing library (page 2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bradshaw with Kannan and Grifski such that the one or more components, to determine the randomized parameter by using the pseudo-random vector generator, are configured to determine the randomized parameter based on adding a value generated by the pseudo-random vector generator to a minimum value associated with the randomized parameter in order to take advantage of an existing library (id.).
Response to Arguments
Applicant’s arguments, see pages 10-11, filed 3 April 2026, with respect to the rejections of the claims have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Bradshaw, which the Examiner had expressed concerns about during the interview.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 27 April 2026
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