DETAILED ACTION
Claims 1-20 are present for examination.
Claims 1-4, 8-11, 13, 15-17 and 19 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/21/2026 and 06/03/2026 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 4-8 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7-8 of copending Application No. 17/958,222 in view of Chaudhuri et al. (US7,007,039).
Claim 1 of the present application corresponds to claim 1 of the ‘222 application, where “An apparatus…” corresponds to claim 1, line 1 of the ‘222 application; “a memory interface…” corresponds to claim 1, line 2 of the ‘222 application; “circuitry to…” corresponds to claim 1, line 3 of the ‘222 application; “provide a number of pages with access counts…” corresponds to claim 1, lines 4-6 of the ‘222 application; and “migrate data of pages from a far memory…” corresponds to claim 1, lines 10-11 of the ‘222 application.
The ’222 application does not teach based on a distribution of access counts in the histogram being a first level, reduce the configured access count ranges of the different buckets of the histogram.
However, Chaudhuri et al. teaches a bucket b with frequency f(b)=100 is shown. The result stream for a query q indicates that T.sub.b=90 tuples that lie within the part of bucket b that is touched by query q, q.andgate.b. This means that bucket b.sub.1 is significantly skewed, since 90% of its tuples are located in a small fraction of its volume. The accuracy of the histogram is improved if a new bucket b.sub.nis created (i.e., access frequency mof a bucket is reduced by creating a new bucket and “partitioning” the bucket accesses) (see Fig. 5 and column 6, lines 61-67 and column 7, lines 1-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by the ‘222 application to include the above mentioned to improve performance by allowing buckets to be nested and tunes the histogram to the specific query workload (see Chaudhuri, column 9, lines 49-55).
Claim 7 of the present application corresponds to claim 7 of the ‘222 application, where “wherein the memory interface is to provide access to a memory device…” corresponds to claim 7, lines 1-2 of the ‘222 application.
Claim 8 of the present application corresponds to claim 8 of the ‘222 application, where “a host system coupled to the memory interface…” corresponds to claim 8, lines 1-2 of the ‘222 application.
This is a provisional nonstatutory double patenting rejection.
Claims 2-3 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over copending Application No. 17/958,222 and Chaudhuri et al. (US7,007,039) in view of Jayasena (US2021/0182262).
Claim 2: The ‘222 application and Chaudhuri et al. does not teach wherein the first level comprises a first percentage of pages being within a first number of the buckets.
However, Jayasena et al. teaches hash table logic further includes a slot access counter structure that produces tracking data that represents a number of times each slot in a bucket within the first set of frequently-accessed buckets of the hash table and the second set of less frequently-accessed buckets of the hash table have been accessed. In certain implementations, the hash table logic moves an entry from the second set of less frequently-accessed buckets to the first set of frequently-accessed buckets and vice versa based on the tracking data (see paragraph 25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by the ‘222 application and Chaudhuri et al. to include the above mentioned to can improve latency (see Jayasena, paragraph 45).
Claim 3: The ‘222 application and Chaudhuri et al. does not teach wherein the first level comprises a majority of pages being within a first number of the buckets.
However, Jayasena et al. teaches hash table logic further includes a slot access counter structure that produces tracking data that represents a number of times each slot in a bucket within the first set of frequently-accessed buckets of the hash table and the second set of less frequently-accessed buckets of the hash table have been accessed. In certain implementations, the hash table logic moves an entry from the second set of less frequently-accessed buckets to the first set of frequently-accessed buckets and vice versa based on the tracking data (see paragraph 25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by the ‘222 application and Chaudhuri et al. to include the above mentioned to can improve latency (see Jayasena, paragraph 45).
This is a provisional nonstatutory double patenting rejection.
Claims 4-6 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over copending Application No. 17/958,222 and Chaudhuri et al. (US7,007,039) in view of Balachandran et al. (US2022/0342815).
Claim 4: The ‘222 application and Chaudhuri et al. do not teach wherein the second level is to set a number of page access counts that trigger migration of the data of the pages associated with the first bucket to the near memory device.
However, Balachandran et al. teaches wherein the second level is to set a number of page access counts that trigger migration of the data of the pages to the far memory device (see paragraph 38-40; If (at block 502) the evicted data is not also located in a bucket 118.sub.i, and (at block 506) the first buffer 404.sub.1 is full, then control proceeds to FIG. 6 to move data from the first buffer 404.sub.1 to the first circular buffer 402.sub.1 of the first bucket 400.sub.1. After freeing space in the buffer 404.sub.1 (at block 508) or if the first buffer 404.sub.1 is not full (from the No branch of block 506), the evicted data is copied (at block 510) to the first buffer 404.sub.1… data evicted from the memory 116 may be added to a bucket 118.sub.i associated with a threshold access range including the access count of the evicted data (i.e., hot data evicted from first level memory device is moved to one of the buckets based on the access count determined).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by ‘222 application and Chaudhuri et al. to include the above mentioned to improve the performance of writing data from the first level memory to the second level memory (see Balachandran, paragraph 20).
Claim 5: The ‘222 application and Chaudhuri et al. do not teach comprising the near memory coupled to the memory interface, wherein the near memory is to store the pages.
However, Balachandran et al. teaches the near memory coupled to the memory interface (see paragraph 23; a local memory interface may be used to communicate with the first level memory device 116, such as for a DRAM, and a storage device interface may be used to communicate with the buckets comprising lower level memory devices, such as Non-Volatile Memory Express (NVME) to communicate with flash memory and SSDs), wherein the near memory is to store the pages (see paragraph 5 and 43; data is copied (at block 706) to the first level memory device 116).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by ‘222 application and Chaudhuri et al. to include the above mentioned to improve the performance of writing data from the first level memory to the second level memory (see Balachandran, paragraph 20).
Claim 6: The ‘222 application and Chaudhuri et al. do not teach wherein the far memory comprises a memory pool.
However, Balachandran et al. teaches wherein the far memory comprises a memory pool (see paragraph 3 and 24; buckets 118.sub.1 . . . 118.sub.n may comprise lower level memory devices, such as non-volatile random access memory (NVRAM)… flash memory may be managed as a second memory pool)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by ‘222 application and Chaudhuri et al. to include the above mentioned to improve the performance of writing data from the first level memory to the second level memory (see Balachandran, paragraph 20).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-6, 8-9, 11-12, 14-15, 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815) in view of Chaudhuri et al. (US7,007,039).
With respect claim 1, Balachandran et al. teaches a memory interface (see paragraph 23; memory interface) comprising a host interface (see paragraph 30; interface) and circuitry, wherein the circuitry is to:
determine a second level indicative of page access counts associated with the first bucket(see paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 if its access count 206 is greater than the threshold access count 308 (i.e., bucket with highest access count is determined)); and
migrate data of pages associated with the first bucket from a far memory to a near memory based on the second level (see paragraph 22; one of multiple buckets 118.sub.1 . . . 118.sub.n comprising distinct regions of physical memory devices. The buckets 118.sub.1 . . . 118.sub.n may each have a bucket buffer 120.sub.1 . . . 120.sub.n to buffer data to aggregate into larger data objects before writing to the associated bucket 118.sub.1 . . . 118.sub.n. Also, in paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 (i.e., near memory) if its access count 206 is greater than the threshold access count 308 (i.e., data is moved from buckets to first level memory device based on the access count determined)).
Balachandran et al. does not teach based on a distribution of access counts in the histogram being a first level, change a configured access count range of a first bucket to reduce the configured access count ranges of the first buckets of the histogram, wherein the buckets of the histogram include the first bucket.
However, Chaudhuri et al. teaches a bucket b with frequency f(b)=100 is shown. The result stream for a query q indicates that T.sub.b=90 tuples that lie within the part of bucket b that is touched by query q, q.andgate.b. This means that bucket b.sub.1 is significantly skewed, since 90% of its tuples are located in a small fraction of its volume. The accuracy of the histogram is improved if a new bucket b.sub.nis created (i.e., access frequency mof a bucket is reduced by creating a new bucket and “partitioning” the bucket accesses) (see Fig. 5 and column 6, lines 61-67 and column 7, lines 1-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Chaudhuri et al. to include the above mentioned to improve performance by allowing buckets to be nested and tunes the histogram to the specific query workload (see Chaudhuri, column 9, lines 49-55).
With respect claim 4, Balachandran et al. teaches wherein the second level is to set a number of page access counts that trigger migration of the data of the pages associated with the first bucket to the near memory device (see paragraph 38-40; If (at block 502) the evicted data is not also located in a bucket 118.sub.i, and (at block 506) the first buffer 404.sub.1 is full, then control proceeds to FIG. 6 to move data from the first buffer 404.sub.1 to the first circular buffer 402.sub.1 of the first bucket 400.sub.1. After freeing space in the buffer 404.sub.1 (at block 508) or if the first buffer 404.sub.1 is not full (from the No branch of block 506), the evicted data is copied (at block 510) to the first buffer 404.sub.1… data evicted from the memory 116 may be added to a bucket 118.sub.i associated with a threshold access range including the access count of the evicted data (i.e., hot data evicted from first level memory device is moved to one of the buckets based on the access count determined).
With respect claim 5 Balachandran et al. teaches the near memory coupled to the memory interface (see paragraph 23; a local memory interface may be used to communicate with the first level memory device 116, such as for a DRAM, and a storage device interface may be used to communicate with the buckets comprising lower level memory devices, such as Non-Volatile Memory Express (NVME) to communicate with flash memory and SSDs), wherein the near memory is to store the pages (see paragraph 5 and 43; data is copied (at block 706) to the first level memory device 116).
With respect claim 6, Balachandran et al. teaches wherein the far memory comprises a memory pool (see paragraph 3 and 24; buckets 118.sub.1 . . . 118.sub.n may comprise lower level memory devices, such as non-volatile random access memory (NVRAM)… flash memory may be managed as a second memory pool)
With respect claim 8, Balachandran et al. teaches a host system coupled to the memory interface (see paragraph 31; the cache controller 104 and storage controller 105 implemented in a host node 102 may comprise blade servers in a host 102 server chassis or comprise separate rack servers or server boxes that communicate over a local network or are implemented on a PCI card and communicate over a bus interface), wherein the host system is to access the near memory by the memory interface (see paragraph 23; storage controller 105 may communicate over one or more bus interfaces 122. Further, the integrated cache manager 114 may communicate over different types and separate bus and device interfaces for different of the memory devices 116, 118.sub.1 . . . 118.sub.n).
With respect claim 9, Balachandran et al. teaches instructions stored thereon, that if executed by one or more processors (see paragraph 58 and 61; may be provided to a processor of a general purpose computer, to produce a machine, such that the instructions, which execute via the processor of the computer create means for implementing the functions/acts specified in the flowchart), cause the one or more processors to:
execute a device driver to configure circuitry in a memory interface (see paragraph 65-66; other hardware and/or software components could be used in conjunction with computer system/server 1202. Examples, include device drivers) to:
determine a second level indicative of page access counts in a bucket of the buckets of the histogram (see paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 if its access count 206 is greater than the threshold access count 308 (i.e., bucket with highest access count is determined); and
migrate data of pages associated with the bucket from a far memory to a near memory based on the second level (see paragraph 22; one of multiple buckets 118.sub.1 . . . 118.sub.n comprising distinct regions of physical memory devices. The buckets 118.sub.1 . . . 118.sub.n may each have a bucket buffer 120.sub.1 . . . 120.sub.n to buffer data to aggregate into larger data objects before writing to the associated bucket 118.sub.1 . . . 118.sub.n. Also, in paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 (i.e., near memory) if its access count 206 is greater than the threshold access count 308 (i.e., data is moved from buckets to first level memory device)).
Balachandran et al. does not teach based on a distribution of access counts in a histogram being a first level, change an access count range to reduce the configured access count ranges of the different buckets of the histogram.
However, Chaudhuri et al. teaches a bucket b with frequency f(b)=100 is shown. The result stream for a query q indicates that T.sub.b=90 tuples that lie within the part of bucket b that is touched by query q, q.andgate.b. This means that bucket b.sub.1 is significantly skewed, since 90% of its tuples are located in a small fraction of its volume. The accuracy of the histogram is improved if a new bucket b.sub.nis created (i.e., access frequency mof a bucket is reduced by creating a new bucket and “partitioning” the bucket accesses) (see Fig. 5 and column 6, lines 61-67 and column 7, lines 1-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Chaudhuri et al. to include the above mentioned to improve performance by allowing buckets to be nested and tunes the histogram to the specific query workload (see Chaudhuri, column 9, lines 49-55).
With respect claim 11, Balachandran et al. teaches wherein the second level is to set a number of page access counts that trigger migration of the data of the pages to the near memory (see paragraph 22; one of multiple buckets 118.sub.1 . . . 118.sub.n comprising distinct regions of physical memory devices. The buckets 118.sub.1 . . . 118.sub.n may each have a bucket buffer 120.sub.1 . . . 120.sub.n to buffer data to aggregate into larger data objects before writing to the associated bucket 118.sub.1 . . . 118.sub.n. Also, in paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 (i.e., near memory) if its access count 206 is greater than the threshold access count 308 (i.e., data is moved from buckets to first level memory device)).
With respect claim 12, Balachandran et al. teaches wherein the far memory comprises a memory pool (see paragraph 3 and 24; buckets 118.sub.1 . . . 118.sub.n may comprise lower level memory devices, such as non-volatile random access memory (NVRAM)… flash memory may be managed as a second memory pool).
With respect claim 14, Balachandran et al. teaches wherein: the far memory has a lower latency and/or lower bandwidth than the near memory (see paragraph 3 and 24; first level memory 116 may comprise a high cost and very low latency device (i.e., near memory) such as a Dynamic Random Access Memory (DRAM)… buckets (i.e., far memory) may comprise lower level memory devices, such as non-volatile random access memory (NVRAM) (i.e., NVRAM has lower bandwidth than DRAM)).
With respect claim 15, Balachandran et al. teaches determining a second level indicative of page access counts in a bucket of the buckets of the histogram (see paragraph 35; data in the highest bucket 400.sub.4 having the highest threshold access count 308 may be moved back to the first level memory 116 if its access count 206 is greater than the threshold access count 308 (i.e., bucket with highest access count is determined)); and
based on the second level, causing migration of data associated with the bucket (see paragraph 43; hottest data is stored in first level memory device) from a far memory device to a near memory device (see paragraph 38-40; If (at block 502) the evicted data is not also located in a bucket 118.sub.i, and (at block 506) the first buffer 404.sub.1 is full, then control proceeds to FIG. 6 to move data from the first buffer 404.sub.1 to the first circular buffer 402.sub.1 of the first bucket 400.sub.1. After freeing space in the buffer 404.sub.1 (at block 508) or if the first buffer 404.sub.1 is not full (from the No branch of block 506), the evicted data is copied (at block 510) to the first buffer 404.sub.1… data evicted from the memory 116 may be added to a bucket 118.sub.i associated with a threshold access range including the access count of the evicted data (i.e., hot data evicted from first level memory device is moved to one of the buckets based on the access count determined)).
Balachandran et al. does not teach based on a distribution of access counts in a histogram being a first level, change an access count ranges to reduce the access count ranges of buckets of the histogram.
However, Chaudhuri et al. teaches a bucket b with frequency f(b)=100 is shown. The result stream for a query q indicates that T.sub.b=90 tuples that lie within the part of bucket b that is touched by query q, q.andgate.b. This means that bucket b.sub.1 is significantly skewed, since 90% of its tuples are located in a small fraction of its volume. The accuracy of the histogram is improved if a new bucket b.sub.nis created (i.e., access frequency mof a bucket is reduced by creating a new bucket and “partitioning” the bucket accesses) (see Fig. 5 and column 6, lines 61-67 and column 7, lines 1-20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Chaudhuri et al. to include the above mentioned to improve performance by allowing buckets to be nested and tunes the histogram to the specific query workload (see Chaudhuri, column 9, lines 49-55).
With respect claim 17, Balachandran et al. teaches wherein the second level is to set a number of page access counts that trigger migration of the data of the pages to the near memory device (see paragraph 38-40; If (at block 502) the evicted data is not also located in a bucket 118.sub.i, and (at block 506) the first buffer 404.sub.1 is full, then control proceeds to FIG. 6 to move data from the first buffer 404.sub.1 to the first circular buffer 402.sub.1 of the first bucket 400.sub.1. After freeing space in the buffer 404.sub.1 (at block 508) or if the first buffer 404.sub.1 is not full (from the No branch of block 506), the evicted data is copied (at block 510) to the first buffer 404.sub.1… data evicted from the memory 116 may be added to a bucket 118.sub.i associated with a threshold access range including the access count of the evicted data (i.e., hot data evicted from first level memory device is moved to one of the buckets based on the access count determined)).
With respect claim 20, Balachandran et al. teaches wherein: the far memory has a lower latency and/or lower bandwidth than a latency and/or bandwidth associated with the near memory (see paragraph 3 and 24; first level memory 116 may comprise a high cost and very low latency device (i.e., near memory) such as a Dynamic Random Access Memory (DRAM)… buckets (i.e., far memory) may comprise lower level memory devices, such as non-volatile random access memory (NVRAM) (i.e., NVRAM has lower bandwidth than DRAM)).
Claim(s) 2-3, 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815) and Chaudhuri et al. (US7,007,039) as applied to claims 1, 9 and 15 above, and further in view of Jayasena (US2021/0182262).
With respect claim 2, Balachandran et al. and Chaudhuri et al. do not teach wherein the first level comprises a first percentage of pages being within a first number of the buckets of the histogram.
However, Jayasena et al. teaches hash table logic further includes a slot access counter structure that produces tracking data that represents a number of times each slot in a bucket within the first set of frequently-accessed buckets of the hash table and the second set of less frequently-accessed buckets of the hash table have been accessed. In certain implementations, the hash table logic moves an entry from the second set of less frequently-accessed buckets to the first set of frequently-accessed buckets and vice versa based on the tracking data (see paragraph 25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to can improve latency (see Jayasena, paragraph 45).
With respect claim 3, Balachandran et al. and Chaudhuri et al. do not teach wherein the first level comprises a majority of pages being within a first number of the buckets of the histogram.
However, Jayasena et al. teaches hash table logic further includes a slot access counter structure that produces tracking data that represents a number of times each slot in a bucket within the first set of frequently-accessed buckets of the hash table and the second set of less frequently-accessed buckets of the hash table have been accessed. In certain implementations, the hash table logic moves an entry from the second set of less frequently-accessed buckets to the first set of frequently-accessed buckets and vice versa based on the tracking data (see paragraph 25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to can improve latency (see Jayasena, paragraph 45).
With respect claim 10, Balachandran et al. and Chaudhuri et al. do not teach wherein the first level comprises a first percentage of pages being within a first number of the buckets.
However, Jayasena et al. teaches hash table logic further includes a slot access counter structure that produces tracking data that represents a number of times each slot in a bucket within the first set of frequently-accessed buckets of the hash table and the second set of less frequently-accessed buckets of the hash table have been accessed. In certain implementations, the hash table logic moves an entry from the second set of less frequently-accessed buckets to the first set of frequently-accessed buckets and vice versa based on the tracking data (see paragraph 25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to can improve latency (see Jayasena, paragraph 45).
With respect claim 16, Balachandran et al. and Chaudhuri et al. do not teach wherein the first level comprises a first percentage of pages being within a first number of the buckets.
However, Jayasena et al. teaches hash table logic further includes a slot access counter structure that produces tracking data that represents a number of times each slot in a bucket within the first set of frequently-accessed buckets of the hash table and the second set of less frequently-accessed buckets of the hash table have been accessed. In certain implementations, the hash table logic moves an entry from the second set of less frequently-accessed buckets to the first set of frequently-accessed buckets and vice versa based on the tracking data (see paragraph 25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to can improve latency (see Jayasena, paragraph 45).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815) and Chaudhuri et al. (US7,007,039) as applied to claim 1 above, and further in view of Hsu et al. (US2022/0164118).
With respect claim 7, Balachandran et al. and Chaudhuri et al. do not teach wherein the memory interface is to provide access to a memory device in a manner consistent at least with Compute Express Link (CXL).
However, Hsu et al. teaches wherein the pooled memory devices may be limited based on a number of upstream ports or a CXL bus interface between the memory controller systems and the corresponding computing nodes (see paragraphs 105 and 125).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to improve performance of the apparatus (see Hsu, paragraphs 44 and 106).
Claim(s) 13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815) and Chaudhuri et al. (US7,007,039) as applied to claims 9 and 15 above, and further in view of Wei et al. (US2022/0382477).
With respect claim 13, Balachandran et al. teaches wherein: the memory interface provides a memory interface to the near memory (see paragraph 23; memory interface).
Balachandran et al. and Chaudhuri et al. do not teach to provide the histogram by counting a number of accesses to the near memory over a duration of time.
However, Wei et al. teaches wherein records 42 include metrics such as a bucket or container name, an access date, and an access counter. Access activity monitor 30 creates a new record 42 to track the first access activity of a data object 38 in a given period, e.g., in a sequential period such as on consecutive days. In particular cases, access activity monitor 30 creates a new record 42 to track the first access activity of a data object 38 in a period (e.g., in a day). In these cases, for a given record 42, the access activity monitor 30 can update the access counter (FIG. 5) for individual access activities for the data object 38 within the period (see paragraph 73) … In some cases, the given period is a daily period such as an approximately 24-hour period (i.e., given period may be adjusted) (see paragraph 39).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to significantly reduce latency in data object retrieval, as well as reduce consumption of storage resources (see Wei, paragraph 29).
With respect claim 18, Balachandran et al. teaches a memory interface to the near memory (see paragraph 23; memory interface).
Balachandran et al. and Chaudhuri et al. do not teach providing the histogram by counting a number of accesses to the near memory over a duration of time.
However, Wei et al. teaches wherein records 42 include metrics such as a bucket or container name, an access date, and an access counter. Access activity monitor 30 creates a new record 42 to track the first access activity of a data object 38 in a given period, e.g., in a sequential period such as on consecutive days. In particular cases, access activity monitor 30 creates a new record 42 to track the first access activity of a data object 38 in a period (e.g., in a day). In these cases, for a given record 42, the access activity monitor 30 can update the access counter (FIG. 5) for individual access activities for the data object 38 within the period (see paragraph 73) … In some cases, the given period is a daily period such as an approximately 24-hour period (i.e., given period may be adjusted) (see paragraph 39).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Balachandran et al. and Chaudhuri et al. to include the above mentioned to significantly reduce latency in data object retrieval, as well as reduce consumption of storage resources (see Wei, paragraph 29).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balachandran et al. (US2022/0342815), Chaudhuri et al. (US7,007,039) and Wei et al. (US2022/0382477) as applied to claim 15 and 18 above, and further in view of Hsu et al. (US2022/0164118).
With respect claim 19, Balachandran et al., Chaudhuri et al. and Wei et al. do not teach wherein the memory interface providing access to the near memory device in a manner consistent at least with Compute Express Link (CXL).
However, Hsu et al. teaches wherein the pooled memory devices may be limited based on a number of upstream ports or a CXL bus interface between the memory controller systems and the corresponding computing nodes (see paragraphs 105 and 125).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Balachandran et al., Chaudhuri et al. and Wei et al. to include the above mentioned to improve performance of the apparatus (see Hsu, paragraphs 44 and 106).
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection, necessitated by amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ganguly et al. (US2022/0214825) teaches a dynamically changing access counter threshold calculated dynamically based on a static threshold that is set for the system, and responsive to determining that the number of times exceeds the dynamically changing access counter threshold, migrating the unit of data from the far memory to the near memory (see Abstract).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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