Detailed Action
Summary
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office action is in response to the application filed on December 23, 2024.
2. Claim 1 is pending and has been examined.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 12/23/2024,07/25/2025,08/01/2025 and 02/04/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
4. Drawings are submitted on 12/23/2024 are acceptable.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a) (1) and 102(a) (2) as being anticipated by Kasturi “20160154037”.
In re to claim 1, Kasturi discloses a system ( Fig.6 shows a diagram illustrating connectivity between multiple driver circuits and a corresponding control circuit according power supply of Fig.1) comprising: a voltage regulator controller (control circuitry 640) configured to maintain a phase voltage (Fig. 6 shows drivers pin are configured to transmit signals the phase voltage #1-#3 of power supply); and a driver ( driver circuitry 650-1, 650-2 and 650-3) associated with the phase voltage (driver configured to the pin phase) , the driver (650-1, 650-2 and 650-3) including a first signal line communicatively coupled to the voltage regulator controller (VSEN1 line is coupled to drivers 650-1-650-3 pin SW to sense the output voltage via inductors L1-L3) , wherein the driver is configured to transmit a multiplexed signal on the first signal line to the voltage regulator controller (communication bus 655 and communication link 157 are coupled to the controller 640 to transmit signals) .
Contact Information
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Heineman “20100013304” the present invention discloses a distributed power management system may include a digital communication bus and a plurality of POL (point-of-load) regulators coupled to the communication bus and configured in a current sharing arrangement in which each POL regulator of the plurality of POL regulators has a respective output stage coupled to a common load and configured to generate a respective output current.
Zhang “20170248996” This application relates to information handling systems, and more particularly to multi-phase voltage regulator (VR) circuitry and methods for controlling such circuitry.
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/SISAY G TIKU/
Primary Examiner, Art Unit 2838
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