DETAILED ACTION
This office action is in response to the application filed on 12/23/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/23/2024 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims 8-9 and 14. Therefore, the “wherein when the output feedback circuit is configured to be the cut off connection state, the fourth pin is configured to be disconnected from the output voltage”, “wherein when the output feedback circuit is configured to be the cut off connection state, the secondary control circuit is configured to be disconnected from the output voltage” and “overload protection function” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiners Note: The Vout signal is connected through the VIN port in circuit 13.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 6-7, 10, 13 and 19 are objected to because of the following informalities: Claims 6, 10 and 19 last line “to be a cut off connection state” should be “to be in a cut off connection state”. Claims 7 and 13 line 3, “to be a short to ground state” should be “to be in a short to ground state”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites “in response to the output voltage decreasing to a second output threshold, the output feedback circuit is configured to be a normal connection state”. However, it is not clear what the applicant meant because the specification par. 45 mentions that when this operation happens the state is the short to ground state not the normal state. Also, see step s103 in figure 4 and related claims 7 and 13. For purposes of examination the limitations are going to be interpreted as mentioned in the specification and the drawings.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Quigley US 2017/0054376.
Regarding Claim 1, Quigley teaches (Figures 1-2) a control circuit (106a) for a switching converter (Fig. 2) with an output feedback circuit (246 and circuitry at 218), the control circuit comprising: a first pin (PWMD) configured to be coupled to the output feedback circuit to receive an output feedback signal (from 246); a second pin (gate) configured to provide a switch control signal (sent to 236) to control the power operation of the switching converter; a third pin (Vin) configured to be coupled to an auxiliary winding (241) of the switching converter to receive an auxiliary winding voltage signal (from 250) indicative of a voltage across the auxiliary winding (at Vin); a switch control circuit (136 and 148) coupled to the first pin to receive the output feedback signal and configured to generate the switch control signal based on the output feedback signal (see fig. 2); and a sleep mode determining circuit (152-154 and 158) coupled to the third pin (at Vin) to receive the auxiliary winding voltage signal and configured to determine whether to enter a sleep mode based on the auxiliary winding voltage signal (par. 35-37). (For example: Par. 24-37)
Regarding 2, Quigley teaches (Figures 1-2) wherein the sleep mode determining circuit (152-154 and 158) is configured to determine whether to enter the sleep mode based on a slope of the auxiliary winding voltage signal (with operation of 152-154 and 158 , see par. 35-37).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Quigley in view of Lin US 201300033905.
Regarding claim 3, Quigley teaches (Figures 1-2) the sleep mode determining circuit.
Quigley does not teach a sample-and-hold circuit configured to generate a sample-and-hold signal based on the auxiliary winding voltage signal; and a slope detecting circuit configured to detect whether the sample-and-hold signal increases from a low value to a high value within a detect time threshold.
Lin teaches (Figures 16-17) a sample-and-hold circuit (Fig. 16) configured to generate a sample-and-hold signal (s2-s3 and c2-c3) based on the auxiliary winding voltage signal (Vaux); and a slope detecting circuit (rest of circuit 1532) configured to detect whether the sample-and-hold signal increases from a low value to a high value within a detect time threshold (e.g. TL, fig. 17). (For example: Par. 162-171)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Quigley to include a sample-and-hold circuit configured to generate a sample-and-hold signal based on the auxiliary winding voltage signal; and a slope detecting circuit configured to detect whether the sample-and-hold signal increases from a low value to a high value within a detect time threshold, as taught by Lin to provide effective response to output loading changes.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Quigley in view of Li US 20160261198.
Regarding Claims 4-5, Quigley teaches (Figures 1-2) the sleep mode determining circuit.
Quigley does not teach wherein the sleep mode determining circuit is further coupled to the first pin to receive the output feedback signal and configured to determine whether to exit the sleep mode based on the output feedback signal; wherein the sleep mode determining circuit comprises: a comparing circuit configured to compare the output feedback signal with a feedback threshold to determine whether to exit the sleep mode.
Li teaches (Figures 6-7) wherein the sleep mode determining circuit (402) is further coupled to the first pin to receive the output feedback signal (Vfb) and configured to determine whether to exit the sleep mode based on the output feedback signal (UL signal); wherein the sleep mode determining circuit comprises: a comparing circuit (with 41 and 43) configured to compare the output feedback signal with a feedback threshold to determine whether to exit the sleep mode (step 502). (For example: Par. 49-54)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Quigley to include wherein the sleep mode determining circuit is further coupled to the first pin to receive the output feedback signal and configured to determine whether to exit the sleep mode based on the output feedback signal; wherein the sleep mode determining circuit comprises: a comparing circuit configured to compare the output feedback signal with a feedback threshold to determine whether to exit the sleep mode, as taught by Li to reduce large number of components resulting in high power consumption.
Claim(s) 6-7, 10-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Quigley in view of Chung US2013/0241509.
Regarding Claims 6-7, 10 and 13, Quigley teaches (Figures 1-2) the sleep mode determining circuit.
Quigley does not teach wherein during a time period when a load is disconnected from the switching converter, in response to an output voltage of the switching converter decreasing to a first output threshold, the output feedback circuit is configured to be a cut off connection state; wherein during the sleep mode, in response to the output voltage decreasing to a second output threshold, the output feedback circuit is configured to be a short to ground state, wherein the second output threshold is higher than the first output threshold.
Chung teaches (Figures 1-7) wherein during a time period when a load is disconnected from the switching converter (no load, par. 22), in response to an output voltage of the switching converter decreasing to a first output threshold (Vfb sent to 52 and decreasing to Voz), the output feedback circuit is configured to be a cut off connection state (in Deep burst switching mode, see par. 28); wherein during the sleep mode, in response to the output voltage decreasing to a second output threshold (Vozr), the output feedback circuit is configured to be a short to ground state (Sps signal is high, switch 55 is on), wherein the second output threshold is higher than the first output threshold (Voz and Vozr, fig. 6). (For example: Par. 26-27 and 30-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Quigley to include wherein during a time period when a load is disconnected from the switching converter, in response to an output voltage of the switching converter decreasing to a first output threshold, the output feedback circuit is configured to be a cut off connection state; wherein during the sleep mode, in response to the output voltage decreasing to a second output threshold, the output feedback circuit is configured to be a short to ground state, wherein the second output threshold is higher than the first output threshold, as taught by Chung to electrical consumption in devices under no-load condition.
Regarding Claim 10, Quigley teaches (Figures 1-2) a switching converter (Fig. 2) comprising: a voltage converting circuit configured to convert an input voltage into an output voltage (DC to Vout); an output feedback circuit (246 and circuitry in 218) coupled to receive the output voltage and configured to provide an output feedback signal (sent from 246); and a switch control circuit (136 and 148) coupled to the output feedback circuit to receive the output feedback signal and configured to generate a switch control signal (gate) to control the voltage converting circuit. (For example: Par. 24-37)
Quigley does not teach wherein during a time period when a load is disconnected from the switching converter, in response to an output voltage of the switching converter decreasing to a first output threshold, the output feedback circuit is configured to be a cut off connection state.
Chung teaches (Figures 1-7) wherein during a time period when a load is disconnected from the switching converter (no load, par. 22), in response to an output voltage of the switching converter decreasing to a first output threshold (Vfb sent to 52 and decreasing to Voz), the output feedback circuit is configured to be a cut off connection state (in Deep burst switching mode, see par. 28). (For example: Par. 26-27 and 30-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Quigley to include wherein during a time period when a load is disconnected from the switching converter, in response to an output voltage of the switching converter decreasing to a first output threshold, the output feedback circuit is configured to be a cut off connection state, as taught by Chung to electrical consumption in devices under no-load condition.
Regarding Claim 11, Quigley teaches (Figures 1-2) a sleep mode determining circuit (152-154 and 158) coupled to an auxiliary winding (241) of the switching converter to receive an auxiliary winding voltage signal (sent to Vin) indicative of a voltage across the auxiliary winding and configured to determine whether to enter a sleep mode based on a slope of the auxiliary winding voltage signal (with operation of 152-154 and 158 , see par. 35-37). (For example: Par. 24-37)
Claim(s) 8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Quigley in view of Chung US2013/0241509 and further in view of Lee US 20200287454.
Regarding Claims 8 and 14, Quigley teaches (Figures 1-2) a secondary control circuit (218) wherein the secondary control circuit comprises a fourth pin configured to be coupled to the output voltage (V\S).
Quigley does not teach wherein when the output feedback circuit is configured to be the cut off connection state, the fourth pin is configured to be disconnected from the output voltage.
Lee teaches (Figures 2 and 5-8) wherein when the output feedback circuit is configured to be the cut off connection state (525 off), the fourth pin is configured to be disconnected from the output voltage (with step 250). (For example: Par. 32-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Quigley to include wherein when the output feedback circuit is configured to be the cut off connection state, the fourth pin is configured to be disconnected from the output voltage, as taught by Lee to reduce power consumption to the load interface and protect the load.
Regarding Claim 15, Quigley teaches (Figures 1-2) a circuit.
Quigley does not teach a power delivery controller configured to detect whether the load is disconnected from the switching converter and coupled to the output feedback circuit to configure the state of the output feedback circuit..
Lee teaches (Figures 2 and 5-8) a power delivery controller (with 720 and 710) configured to detect whether the load is disconnected from the switching converter and coupled to the output feedback circuit (at 550) to configure the state of the output feedback circuit (see fig. 8). (For example: Par. 56-65)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Quigley to include a power delivery controller configured to detect whether the load is disconnected from the switching converter and coupled to the output feedback circuit to configure the state of the output feedback circuit, as taught by Lee to reduce power consumption to the load interface and protect the load.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Quigley in view of Lee US 20200287454.
Regarding Claim 9, Quigley teaches (Figures 1-2) the circuit.
Quigley does not teach wherein when the control circuit enters the sleep mode, an overload protection function is disabled.
Lee teaches (Figures 2 and 5-8) wherein when the control circuit enters the sleep mode (240), an overload protection function is disabled (250). (For example: Par. 33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Quigley to include wherein when the control circuit enters the sleep mode, an overload protection function is disabled, as taught by Lee to reduce power consumption to the load interface and protect the load.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Quigley in view of Chung and further in view of Li US 20160261198.
Regarding Claim 12, Quigley teaches (Figures 1-2) the sleep mode determining circuit.
Quigley does not teach wherein the sleep mode determining circuit is further coupled to the first pin to receive the output feedback signal and configured to determine whether to exit the sleep mode based on the output feedback signal.
Li teaches (Figures 6-7) wherein the sleep mode determining circuit (402) is further coupled to the first pin to receive the output feedback signal (Vfb) and configured to determine whether to exit the sleep mode based on the output feedback signal (UL signal). (For example: Par. 49-54)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Quigley to include wherein the sleep mode determining circuit is further coupled to the first pin to receive the output feedback signal and configured to determine whether to exit the sleep mode based on the output feedback signal, as taught by Li to reduce large number of components resulting in high power consumption.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khamesra US 20250103119 in view of Chung 20130241509.
Regarding Claim 16, Khamesra teaches (Figures 1-4) a control circuit (102-104) for a switching converter (see fig. 1) with an output feedback circuit (feedback circuitry at fig. 1b producing feedback signals), the control circuit comprising: a first pin configured to be coupled to the output feedback circuit (feedback circuitry) to receive an output feedback signal (receiving Vbus signal); a second pin (gdh or gdl) configured to provide a switch control signal (output of gdh or gdl) to control the power operation of the switching converter; a primary turning-on control circuit (at 104 producing PWM signal sent to 174) coupled to the first pin to receive the output feedback signal and configured to generate a primary turning-on signal (PWM) based on the output feedback signal (Vbus); an isolation circuit (174) configured to generate a sync signal pulse (Puls in) electrically isolated from the primary turning-on signal; a logic circuit (at 186 see fig. 1a) configured to generate the switch control signal based on the sync signal pulse.
(For example: Par. 19-24 and 45)
Khamesra does not teach a sleep mode determining circuit configured to determine whether to enter a sleep mode based on the switch control signal.
Chung teaches (Figures 1-7) a sleep mode determining circuit (52) configured to determine whether to enter a sleep mode based on the switch control signal (sw sent to 52). (For example: Par. 24-25 and 28-29)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Khamesra to include a sleep mode determining circuit configured to determine whether to enter a sleep mode based on the switch control signal, as taught by Chung to electrical consumption in devices under no-load condition.
Regarding Claim 17, Khamesra teaches (Figures 1-4)wherein in response to a duration of the switching converter stopping switching reaches a time threshold (see fig. 4, at times 402 and t1), the control circuit is configured to enter the sleep mode (LPM). (For example: Par. 19-24 and 41-43)
Regarding Claim 18, Khamesra teaches (Figures 1-4) wherein the sleep mode determining (210) circuit is further configured to determine whether to exit the sleep mode based on the sync signal pulse (PWM signal), wherein in response to the sync signal pulse appearing, the control circuit is configured to exit the sleep mode (see fig. 4, at 404 and wakeup state). (For example: Par. 19-24 and 41-43)
Regarding Claim 19-20, Khamesra teaches (Figures 1-4) the circuit.
Khamesra does not teach wherein during a time period when a load is disconnected from the switching converter, in response to an output voltage of the switching converter decreasing to a first output threshold, the output feedback circuit is configured to be a cut off connection state; wherein during the sleep mode, in response to the output voltage decreasing to a second output threshold, the output feedback circuit is configured to be a short to ground state, wherein the second output threshold is higher than the first output threshold.
Chung teaches (Figures 1-7) wherein during a time period when a load is disconnected from the switching converter (no load, par. 22), in response to an output voltage of the switching converter decreasing to a first output threshold (Vfb sent to 52 and decreasing to Voz), the output feedback circuit is configured to be a cut off connection state (in Deep burst switching mode, see par. 28); wherein during the sleep mode, in response to the output voltage decreasing to a second output threshold (Vozr), the output feedback circuit is configured to be a short to ground state (Sps signal is high, switch 55 is on), wherein the second output threshold is higher than the first output threshold (Voz and Vozr, fig. 6). (For example: Par. 26-27 and 30-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Khamersa to include wherein during a time period when a load is disconnected from the switching converter, in response to an output voltage of the switching converter decreasing to a first output threshold, the output feedback circuit is configured to be a cut off connection state; wherein during the sleep mode, in response to the output voltage decreasing to a second output threshold, the output feedback circuit is configured to be a short to ground state, wherein the second output threshold is higher than the first output threshold, as taught by Chung to electrical consumption in devices under no-load condition.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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