DETAILED ACTION
The instant action is in response to application 24 December 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to for the following informalities:
The title does not seem to emphasize the point of the claimed invention. Examiner suggests “Reference Current Generating Circuit and Calibration without External Testing Equipment”.
There is a Taiwanese copending application. It appears the Taiwanese application has the oldest filing date. As such, it is required for the copending application with the oldest filing date to be included in the background section. It is also ordinary and customary to include other copending applications filing dates and publication dates (if available).
¶2 appears to have some unnecessary verbosity, which is generally not permitted in 35 USC 112(a). For example, sentence 1 could be revised: “Making a reference current generating circuit inside an integrated circuit generate requires calibration to generate a reference current that is less affected by temperature, and to determine its parameters.” Also, sentence 3 “The output padcan increase the manufacturing costs and the packaging difficulty.” Sentence 4 could also be revised “Since current reference currents are require high accuracy which increases .”
¶3 also appears to have unnecessary verbosity. “The present invention provides a reference current generating circuit with an automatic calibration mechanism that s calibration of a reference current without external test machines, to address the above-mentioned issues.”
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Taiwan on 3 January 2024.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 11216021) in view of Walker (US 9766135).
As to claim 1, Huang discloses (see image with item matching below) a reference current generating circuit, comprising: a temperature sensing circuit, arranged to sense a temperature of the reference current generating circuit to provide a voltage; an adjustable resistor, coupled to the temperature sensing circuit, and arranged to generate a reference current according to the voltage; a current mirror, arranged to generate an output current according to the reference current; and a calibration circuit, comprising: a resistor,
Huang does not disclose arranged to generate an output voltage according to the output current; a comparator, arranged to compare the output voltage with a reference voltage to generate a comparison result; and a control circuit, arranged to sequentially generate and transmit multiple control signals to the adjustable resistor, and determine an optimal resistance value of the adjustable resistor and a final control signal corresponding to the optimal resistance value according to the comparison result.
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Walker (Fig. 3b) teaches a calibration circuit, comprising: a resistor (320-2), arranged to generate an output voltage (Temp 2) according to the output current; a comparator (300-2), arranged to compare the output voltage with a reference voltage (VBGREF) to generate a comparison result; and a control circuit, arranged to sequentially generate and transmit multiple control signals (HYS1-m(2))to the adjustable resistor, and determine an optimal resistance value of the adjustable resistor and a final control signal corresponding to the optimal resistance value according to the comparison result (Col. 6, lines 45-50 “Variable resistor 320-2 then may provide hysteresis to reset temperature indication signal TEMP2 only after the temperature of the semiconductor device 100 drops a predetermined number of degrees below the predetermined temperature.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use an adjustable resistance as disclosed in Walker to finely tune the temperature circuit.
As to claim 2, Huang in view of Walker teaches wherein the control circuit sequentially generates the multiple control signals to control a resistance value of the adjustable resistor to sequentially increase from a lowest resistance value to a highest resistance value (Walker Fig. 16, item S1620); and when the comparison result switches from a first logical value to a second logical value or switches from the second logical value to the first logical value, the control circuit records a current control signal as the final control signal (Fig. 16, S1670, S1660, S 1694).
As to claim 3, Huang in view of Walker teaches wherein the control circuit sequentially generates the multiple control signals to control a resistance value of the adjustable resistor to sequentially decrease from a highest resistance value to a lowest resistance value (Walker, Fig 16, 1660); and when the comparison result switches from a first logical value to a second logical value or switches from the second logical value to the first logical value, the control circuit records a current control signal as the final control signal (Fig. 16, S1670, S1660, S 1694).
As to claim 4, Huang in view of Walker teaches wherein the control circuit is a digital control circuit ( a comparator is a bit ADC), and the control circuit records the final control final into a non-volatile (Walker Fig. 11(a) Latch) memory.
As to claim 8, Huang in view of Walker teaches wherein the temperature sensing circuit comprises a first transistor; the first transistor comprises a first terminal, a second terminal, and a control terminal; the first terminal is coupled to the current mirror; and the second terminal is coupled to the adjustable resistor (see image above).
As to claim 9, Huang in view of Walker teaches wherein the temperature sensing circuit further comprises a second transistor; the second transistor comprises a first terminal, a second terminal, and a control terminal; the first terminal of the second transistor is coupled to the current mirror; the second terminal of the second transistor is coupled to a grounding voltage; and the control terminal of the second transistor is coupled to the control terminal of the first transistor (see image above).
As to claims 10-13, these appear to be method claims corresponding to apparatus claims 1-4 above and are made obvious for similar reasons per MPEP 2112.02.
Claims 5-7, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 11216021) in view of Walker (US 9766135) and Sakamoto (US 6137717).
As to claim 5, Huang in view of Walker does not teach wherein the control circuit comprises: a flip-flop, arranged to sequentially generate multiple digital codes according to a clock signal; and a decoder, arranged to sequentially receive the multiple digital codes, and generate and transmit the multiple control signals to the adjustable resistor according to the multiple digital codes.
Sakamoto teaches wherein the control circuit comprises: a flip-flop, arranged to sequentially generate multiple digital codes according to a clock signal; and a decoder, arranged to sequentially receive the multiple digital codes, and generate and transmit the multiple control signals to the adjustable resistor according to the multiple digital codes (Fig. 1,& Col. 4, lines 49-55 “The latch clock signal VCK is input to a terminal CK of the D flip-flop 1, while the reset signal Reset-v is input to a terminal R. Also, decode signals Aad-0 to Aad-F indicating absolute addresses of the nonvolatile memory as well as decode signals Rad-0 to Rad-F showing local addresses are input to the sixteen write data registers 7-0 to 7-F, respectively. The decode signals Rad-0 to Rad-F are signals representing the order in which data are stored in the write data registers 7-0 to 7-F.”) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use a read/write scheme as disclosed in Sakamoto to ensure the data integrity (abstract).
As to claim 6, Huang in view of Walker and Sakamoto teaches wherein when a transition of the comparison result occurs, the flip-flop uses a current control signal as the final control signal (this would be taught by the combination, with the signal of Walker being fed into Sakamoto).
As to claim 7, Huang in view of Walker and Sakamoto teaches wherein the control circuit operates in a calibration mode each time the reference current generating circuit is powered on, in order to determine the optimal resistance value of the adjustable resistor and the final control signal (this would be taught by the combination, with the optimization process and signals of Walker being fed into Sakamoto)..
As to claims 14-15, these appear to be method claims corresponding to apparatus claims 5 & 7 above and are made obvious for similar reasons per MPEP 2112.02.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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