DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 6262626 B1 (Bakker), in view of US 20190131943 A1 (Chen) and in further view of US 11228291 B2 (Kusuda) and US 20140232456 A1 (Huijsing).
Regarding Claim 1:
A signal processing device (Bakker: Figs. 2-3), comprising: a first amplifier, configured to generate a second signal according to a first signal (Bakker: para. (3), "The known circuit comprises an amplifier AMP having a differential input 5;6 comprising an input node 5 and an input node 6, and a differential output 7;8...");
two first choppers, embedded between an input end and an output end of the first amplifier, wherein the two first choppers are configured to perform a shifting operation of a first frequency and a shifting back operation of the first frequency, respectively (Bakker: para. (4), first choppers embedded around the amplifier operating at a first (high) frequency, "The input chopper CHPi and the output chopper CHPo receive a high frequency clock signal which is available between a first clock terminal CLKH and a reference terminal GND."; Chen further teaches: [0034]-[0035], "CCIA 300 includes a first chopper 302, a second chopper 304, a first gain stage 306, a second gain stage 308, a capacitive isolation stage 310... Positive input path 322 feeds into an input 326 of first gain stage 306". It would have been obvious to a person of ordinary skill in the art (POSITA) to incorporate Chen’s chopper stabilized amplifier into Bakker’s architecture for reducing input offset and improving amplifier performance);
a second chopper, coupled to the input end of the first amplifier (Bakker: para. (3), a second chopper coupled to the input, "a further input chopper CHPfi... cascaded in between the input terminals 1 and 2 and the input nodes 5 and 6, whereby the further input chopper CHPfi is cascaded in between the input terminals 1 and 2 and the input chopper CHPi."; Huijsing further teaches: [0029]-[0030], an input side chopper, "From the chopper-stabilized amplifier of FIG. 6, the two-path capacitive-coupled amplifier of FIG. 8 is derived. It has a high frequency path through Gm2 that includes the chopper frequency and a low frequency chopper path through Gm5". It would have been obvious to a person of ordinary skill in the art (POSITA) to incorporate Huijsing’s chopper stabilized amplifier into Bakker’s architecture for fast settling of ripple effects), and;
a third chopper, coupled to the output end of the first amplifier (Bakker: para. (3), a third chopper coupled to the output, "a further output chopper CHPfo... cascaded in between the output nodes 7 and 8 and the output terminals 3 and 4, whereby the further output chopper CHPfo is cascaded in between the output chopper CHPo and the output terminals 3 and 4."),
wherein the second chopper is configured to perform a shifting operation of a second frequency, the third chopper is configured to perform a shifting back operation of the second frequency, and the first frequency and the second frequency are different (Bakker: para. (3)-(4), the second/third choppers operate at a different, second frequency, "the further input chopper CHPfi and the further output chopper CHPfo receive a low frequency clock signal... Because the further input chopper CHPfi and the further output chopper CHPfo operate at a relatively low frequency..."; Kusuda further teaches a second frequency injection point, e.g., para. (21), "The multiple signal points include a first signal point along the signal path before the input chopping circuit, and a second signal point along the signal path after the output chopping circuit. Furthermore, in certain implementations, the input offset compensation signal is injected into a portion of the signal path between the amplification circuit and the output chopping circuit". It would have been obvious to a person of ordinary skill in the art (POSITA) to incorporate Kusuda’s the second frequency injection point into Bakker’s architecture for reducing and correcting input signal offset).
Regarding Claim 2, Bakker as modified further teaches:
The signal processing device according to claim 1, further comprising: a fourth chopper, coupled between the output end and the input end of the first amplifier, wherein the fourth chopper is configured to perform the shifting operation of the second frequency, and the third chopper is configured to perform the shifting back operation of the second frequency (Kusuda: para. (59), teaches an offset correction circuit employing a feedback chopper loop "The multi-point sensed offset correction circuit 52 further includes... a chopper circuit 55... an analog filter 56... and an output transconductance amplifier GmCorr".)
Regarding Claim 3, Bakker as modified further teaches:
The signal processing device according to claim 1, further comprising: a second amplifier, coupled to the first amplifier, and configured to generate an output signal according to the second signal; and two fifth choppers, embedded between an input end and an output end of the second amplifier, wherein the two fifth choppers are configured to perform the shifting operation of the first frequency and the shifting back operation of the first frequency (Bakker: para (6), teaches a second amplifier, "the differential signal from the output chopper CHPo is transferred to a single-ended output signal Vout by a further amplifier AMPf.". It is a well-known, standard engineering practice to embed paired choppers (fifth choppers) around subsequent amplifier stages (AMPf) to extend 1/f noise reduction throughout multi-stage signal chains, making this configuration obvious).
Regarding Claim 4, Bakker as modified further teaches:
The signal processing device according to claim 3, further comprising: a DC offset circuit, coupled to the input end of the first amplifier, and configured to adjust a DC voltage level of the first signal according to a control signal (Bakker teaches offset adaptation but lacks a dedicated DC offset adjusting circuit at the input (Kusuda teaches injecting a correction current to adjust DC offset levels, e.g., para. (60), "injects the differential correction current ICorr into the chopper amplifier circuitry 51 such that the differential correction current ICorr is combined with the differential signal current". This renders the addition obvious).
Regarding Claim 5, Bakker as modified further teaches:
The signal processing device according to claim 4, further comprising: a first feedback circuit, coupled between the output end of the second amplifier and the DC offset circuit, and configured to generate the control signal according to the output signal (Kusuda: teaches multi-point feedback generating compensation signals, e.g., para. (60), "multi-point sensed offset correction circuit 52 injects the differential correction current ICorr").
Regarding Claim 6, Bakker as modified further teaches:
The signal processing device according to claim 5, wherein the first feedback circuit comprises: a first low-pass filter, receiving the output signal and generating a first filtered output signal; and a compensation circuit, processing the first filtered output signal to generate a digital control signal based on a calibration signal (Kusuda: teaches a compensation circuit with digital control based on a calibration/sense signal, e.g., para. 68, "a comparator 66, a digital counter 67, and a current DAC (iDAC) 68... The digital counter 67 outputs digital correction data DCorr, which the current DAC 68 uses to generate the differential correction current").
Regarding Claim 7, Bakker as modified further teaches:
The signal processing device according to claim 6, wherein an output end of the compensation circuit has a sixth chopper, the sixth chopper is configured to perform the shifting operation of the second frequency, and the third chopper is configured to perform the shifting back operation of the second frequency (Kusuda: teaches a chopper within the compensation circuit, e.g., para. (59), "a chopper circuit 55 (controlled by the chopping clock signal CLK_CHOP), an analog filter 56".)
Regarding Claim 8, Bakker as modified further teaches:
The signal processing device according to claim 3, further comprising: a second feedback circuit, coupled between the output end of the second amplifier and the input end of the first amplifier, and configured to provide a compensation signal to the input end of the first amplifier according to the output signal (Chen: [0088]-[0089], teaches second feedback auto-zeroing providing compensation to input, "Auto-zeroing circuitry 1314 is electrically coupled to first gain stage outputs 1344 and 1346. Auto-zeroing circuitry 1314 includes a third gain stage 1370, auto-zeroing capacitors 1372 and 1374, and auto-zeroing switching devices 1376 and 1378... Outputs 1384 and 1386 of third gain stage 1370 are electrically coupled to first gain stage outputs 344 and 346, respectively"; Kusuda: teaches compensation injected to input, e.g., para. (60), "As shown in FIG. 6, the multi-point sensed offset correction circuit 52 senses the signal path of the chopper amplifier circuitry 51 at both a differential input to the input chopping circuit 53 and across the series combination... Additionally, the multi-point sensed offset correction circuit 52 injects the differential correction current ICorr into the chopper amplifier circuitry 51").
Regarding Claim 9, Bakker as modified further teaches:
The signal processing device according to claim 8, wherein the second feedback circuit comprises: a second low-pass filter, receiving the output signal and generating a second filtered output signal; and a capacitor pair and a seventh chopper, wherein the capacitor pair and the seventh chopper are serially coupled between the second low-pass filter and the input end of the first amplifier, and configured to generate the compensation signal according to the second filtered output signal, the seventh chopper is configured to perform a shifting operation of the second frequency, and the third chopper is configured to perform a shifting back operation of the second frequency (Huijsing: teaches serially coupled capacitor pairs in chopped loops, e.g., [0030], "On the output side of the coupling capacitors C21,C22 and C51,C52...").
Regarding Claim 10, Bakker as modified further teaches:
The signal processing device according to claim 2, further comprising: a first feedback circuit, coupled between an output end of a second amplifier and the input end of the first amplifier, and configured to provide a first compensation signal to the input end of the first amplifier according to an output signal (Kusuda: As explained for Claims 5 and 8, configuring a first feedback circuit coupled between the output of the second amplifier and the input of the first amplifier to provide a compensation signal is obvious over Kusuda’s multi-point correction applied to Bakker’s multi-stage amplifier structure).
Regarding Claim 14, Bakker as modified further teaches:
The signal processing device according to claim 1, further comprising a mixer, coupled to the input end of the first amplifier, and configured to perform frequency mixing on an input signal to generate the first signal, wherein the second chopper is coupled between an output end of the mixer and the input end of the first amplifier, or, the second chopper is coupled to an input end of the mixer (While Bakker does not explicitly name a "mixer". It is ubiquitous prior art in radio-frequency transceivers to place a frequency mixer at the input of a baseband amplifier. Adding a standard down-conversion mixer before Bakker's chopper amplifier to process modulated RF signals is an obvious combination of standard receiver front-end components).
Regarding Claim 15, Bakker as modified further teaches:
The signal processing device according to claim 1, wherein the first frequency and the second frequency differ by at least two times (Bakker: inherently teaches the first and second frequencies differing by at least two times, e.g., para. (4), stating the first choppers receive a "high frequency clock" and the second/third receive a "low frequency clock". A high vs. low clock frequency distinction inherently necessitates a difference of at least two times (and practically much larger) to prevent frequency aliasing).
Regarding Claim 16, Bakker as modified further teaches:
The signal processing device according to claim 3, further comprising: a filter, coupled between the output end of the first amplifier and the input end of the second amplifier, and the third chopper is coupled between the output end of the filter and the input end of the second amplifier (Bakker teaches filtering unwanted signals. Furthermore, placing a low-pass or band-pass filter between cascaded amplifier stages to remove out-of-band ripple before the next chopping/amplification stage is a fundamental analog design choice that would be obvious to a POSITA refining Bakker’s multi-stage circuit).
Regarding Claim 17, Bakker as modified further teaches:
The signal processing device according to claim 4, further comprising a mixer, coupled to the input end of the first amplifier, and configured to perform frequency mixing on an input signal to generate the first signal, wherein the first signal comprises a first sub-signal, and the DC offset circuit comprises: a first sub-circuit, receiving the first sub-signal, and comprising: a first current source, coupled between a power supply voltage and a first output end of the mixer; a second current source, coupled between the first output end of the mixer and a reference voltage; a third current source, coupled between the power supply voltage and a first input end of the first amplifier; a fourth current source, coupled between the first input end of the first amplifier and the reference voltage; and a first resistor, coupled between the first output end of the mixer and the first input end of the first amplifier, wherein one of the first current source to the fourth current source is controlled by a first control signal of the control signal (Kusuda: teaches generating offset correction through mirrored current generation via a DAC, e.g., para. (68), and (60), "a current DAC (iDAC) 68... the current DAC 68 uses to generate the differential correction current". Implementing this current DAC as a sub-circuit composed of paired current sources and resistors to adjust DC levels is a standard, obvious implementation of Kusuda’s iDAC).
Regarding Claim 18, Bakker as modified further teaches:
The signal processing device according to claim 17, wherein the first signal further comprises a second sub-signal, and the DC offset circuit further comprises: a second sub-circuit, receiving the second sub-signal, and comprising: a fifth current source, coupled between the power supply voltage and a second output end of the mixer; a sixth current source, coupled between the second output end of the mixer and the reference voltage; a seventh current source, coupled between the power supply voltage and a second input end of the first amplifier; an eighth current source, coupled between the second input end of the first amplifier and the reference voltage; and a second resistor, coupled between the second output end of the mixer and the second input end of the first amplifier, wherein one of the fifth current source to the eighth current source is controlled by a second control signal of the control signal (Kusuda: para. (29), the differential input terminals VIN+ VIN-, and para. (59)-(60), differential correction current ICorr requires complementary current sources IS5-IS8 and resistor R62. Obvious differential pair).
Regarding Claim 19, Bakker as modified further teaches:
The signal processing device according to claim 1, further comprising: a first series of capacitors, coupled between a first output end and a first input end of the first amplifier; and a second series of capacitors, coupled between a second output end and a second input end of the first amplifier, wherein the first amplifier, the first series of capacitors, and the second series of capacitors form a capacitively coupled instrumentation amplifier (Huijsing: [0029]-[0031], teaches CCIA capacitor series, e.g., "From the chopper-stabilized amplifier of FIG. 6, the two-path capacitive-coupled amplifier of FIG. 8 is derived... The hybrid-nested Miller compensation scheme with CM31 and CM32 takes care of a straight frequency characteristic" and -, "On the output side of the coupling capacitors C21,C22 and C51,C52... a common mode reference VRef is coupled"; Chen: [0005]-[0006], teaches conventional CCIA with first series capacitors, e.g., "FIG. 1 illustrates a conventional CCIA 100 including a first chopper 102, a second chopper 104, a capacitive isolation stage 106, a first gain stage 108, a second gain stage 110... Capacitive isolation stage 106 is electrically coupled between first chopper 102 and first gain stage 108. Second chopper 104 is electrically coupled between first gain stage 108 and second gain stage 110").
Regarding Claim 20, Bakker as modified further teaches:
A signal transceiver device, comprising: a transmitting circuit, configured to continuously transmit a transmission signal during a first period; and a receiving circuit, configured to continuously receive an input signal during the first period, wherein the input signal is generated by the transmission signal being reflected by an external object, and the receiving circuit comprises: a first amplifier, configured to generate a second signal according to a first signal generated by the input signal; two first choppers, embedded between an input end and an output end of the first amplifier, and configured to perform a shifting operation of a first frequency and a shifting back operation of the first frequency during the first period; a second chopper, coupled to the input end of the first amplifier, and; a third chopper, coupled to the output end of the first amplifier, wherein the second chopper is configured to perform a shifting operation of a second frequency during the first period, the third chopper is configured to perform a shifting back operation of the second frequency during the first period, and the first frequency and the second frequency are different (Claim 1 teaches all limitations of Claim 20 but application In transceiver, where Using Bakker's chopper amplifier inside a signal transceiver device (e.g., continuous wave radar) that continuously transmits and receives reflected input signals during a first period is an obvious intended use. Eliminating the massive DC offsets caused by simultaneous TX-to-RX leakage is the precise problem Bakker’s low-offset amplifier solves, rendering its inclusion in a transceiver obvious).
Allowable Subject Matter
The Claims 11-12 are objected to as being dependent upon a rejected base claim, but are potentially allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 depends on Claim 12, therefore, are objected for the same reasons as Claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHITONG CHEN whose telephone number is (571) 270-1936. The examiner can normally be reached on M-F 9:30am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yuwen Pan can be reached on 571-272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZHITONG CHEN/
Primary Examiner, Art Unit 2649
Prosecution Insights