Prosecution Insights
Last updated: April 19, 2026
Application No. 19/000,832

SYSTEM TO DISPATCH VIDEO DECODING TO DEDICATED HARDWARE RESOURCES

Non-Final OA §DP
Filed
Dec 24, 2024
Examiner
LE, PETER D
Art Unit
2488
Tech Center
2400 — Computer Networks
Assignee
Genetec Inc.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
97%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
491 granted / 613 resolved
+22.1% vs TC avg
Strong +17% interview lift
Without
With
+16.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
35 currently pending
Career history
648
Total Applications
across all art units

Statute-Specific Performance

§101
4.7%
-35.3% vs TC avg
§103
49.5%
+9.5% vs TC avg
§102
17.7%
-22.3% vs TC avg
§112
11.6%
-28.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 613 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA Preliminary Amendment, filed 03/17/2025, has been entered. Claims 1-9 are cancelled. Claims 10-26 are pending. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 10 and 26 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1 and 17 of U.S Patent No. 12,206,947. Claim 17 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 8 of U.S Patent No. 12,206,947. Claim 23 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 14 of U.S Patent No. 12,206,947. Claim 25 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 16 of U.S Patent No. 12,206,947. Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant claims are similar to the claims in the U.S patent to meet the limitations. Table 1 shows comparison between the instant claims and the U.S patent claims. This is a non-provisionally obviousness-type double patenting rejection because the conflicting claims have in fact been patented. Table 1: Comparison of claims in instant Application. 19/000832 vs Application 18/402995 (US Patent 12,206,947) Appl. 19/000832 Appl. 18/402995 (US Pat. 12,206,947) 10. (new) A method for simultaneously decoding a plurality of encoded video streams of one or more video compression formats received at a data interface and displaying each resulting decoded video stream in a predetermined tile of a display in communication with a display control device comprising a graphical user interface (GPU), the display control device in communication with a processing unit (CPU) that is in communication with the data interface, comprising: receiving said plurality of encoded video streams; directing each encoded video stream of the plurality of encoded video streams to be decoded by the GPU; and surveying decoding resources available to determine how many streams can be successfully decoded, anticipate a processing load associated with said plurality of encoded video streams, and in response redirect a given one encoded video stream of the plurality of encoded video streams from being decoded by the GPU to being decoded only by the CPU so as to avoid instantiating too great a number of resources on the GPU. 1 A video decoding system for simultaneously decoding a plurality of encoded video streams of one or more video compression formats and displaying each resulting decoded video stream in a predetermined tile of a display, the system comprising: a data interface configured to receive said plurality of encoded video streams; a processing unit (CPU) in communication with the data interface; a display control device in communication with the CPU, the display control device comprising a graphical processing unit (GPU); and a display in communication with the display control device, memory storing an attribution module configured to direct each encoded video stream of the plurality of encoded video streams to be decoded by the GPU, and survey decoding resources available to determine how many streams can be successfully decoded, anticipate a processing load associated with said plurality of encoded video streams, and in response redirect a given one encoded video stream of the plurality of encoded video streams from being decoded by the GPU to being decoded only by the CPU so as to avoid instantiating too great a number of resources on the GPU. 17. (new) A method for simultaneously decoding a plurality of encoded video streams of one or more video compression formats received at a data interface and displaying each resulting decoded video stream in a predetermined tile of a display in communication with a display control device comprising a graphical user interface (GPU), the display control device in communication with a processing unit (CPU) that is in communication with the data interface, comprising: receiving said plurality of encoded video streams; directing each encoded video stream of the plurality of encoded video streams to be decoded by the GPU; and in response to an oversaturation of existing resources resulting from receiving too large a number of encoded video streams, specifying an additional manipulation operation on at least a subset of said plurality of encoded video streams, the additional manipulation operation adapted to reduce the resource utilization by each encoded video stream in the subset of the plurality of encoded video streams. 8. A video decoding system for simultaneously decoding a plurality of encoded video streams of one or more video compression formats and displaying each resulting decoded video stream in a predetermined tile of a display, the system comprising: a data interface configured to receive said plurality of encoded video streams; a processing unit (CPU) in communication with the data interface; a display control device in communication with the CPU, the display control device comprising a graphical processing unit (GPU); and a display in communication with the display control device, memory storing an attribution module configured to i) direct each encoded video stream of the plurality of encoded video streams to be decoded by the GPU, ii) in response to an oversaturation of existing resources resulting from receiving too large a number of encoded video streams, specifying an additional manipulation operation on at least a subset of said plurality of encoded video streams, the additional manipulation operation adapted to reduce the resource utilization by each encoded video stream in the subset of the plurality of encoded video streams. 17. A video decoding system for simultaneously decoding a plurality of encoded video streams of one or more video compression formats and displaying each resulting decoded video stream in a predetermined tile of a display, the system comprising: a data interface configured to receive said plurality of encoded video streams; a processing unit (CPU) in communication with the data interface; a display control device in communication with the CPU, the display control device comprising a graphical processing unit (GPU); and a display in communication with the display control device, memory storing an attribution module configured to direct each encoded video stream of the plurality of encoded video streams to be decoded by the GPU, and survey decoding resources available to determine how many streams can be successfully decoded, anticipate a processing load associated with said plurality of encoded video streams, and in response direct a given one encoded video stream of the plurality of encoded video streams or a future encoded video stream to being decoded only by the CPU instead of the GPU so as to avoid instantiating too great a number of resources on the GPU. 23. (new) A method for simultaneously decoding a plurality of encoded video streams of one or more video compression formats received at a data interface and displaying each resulting decoded video stream in a predetermined tile of a display, the display being one of a plurality of displays in communication with a display control device comprising a plurality of processing resources, each processing resource of the plurality of processing resources comprising a graphical processing unit (GPU), each display of the plurality of displays being connected to a respective GPU, the display control device in communication with a processing unit (CPU) that is in communication with the data interface, comprising: receiving said plurality of encoded video streams; and directing each encoded video stream of the plurality of encoded video streams to be decoded by a respective GPU according to a load balancing policy determining attribution of the encoded video streams to respective processing resources in accordance with a deployment scenario. 14. A video decoding system for simultaneously decoding a plurality of encoded video streams of one or more video compression formats and displaying each resulting decoded video stream in a predetermined tile of a display, the system comprising: a data interface configured to receive said plurality of encoded video streams; a processing unit (CPU) in communication with the data interface; a display control device in communication with the CPU, the display control device comprising a plurality of processing resources, each processing resource of the plurality of processing resources comprising a graphical processing unit (GPU); and a plurality of displays in communication with the display control device, each display being connected to a respective GPU, memory storing an attribution module configured to direct each encoded video stream of the plurality of encoded video streams to be decoded by a respective GPU according to a load balancing policy determining attribution of the encoded video streams to respective processing resources in accordance with a deployment scenario. 25. (new) A method for simultaneously decoding a plurality of encoded video streams of one or more video compression formats received at a data interface and displaying each resulting decoded video stream in a predetermined tile of a display in communication with a display control device in communication with a processing unit (CPU), the display control device comprising at least one graphical processing unit (GPU), comprising: receiving said plurality of encoded video streams; directing each of the plurality of encoded video streams to be decoded by one of the CPU and the GPU; and detecting that a compression or encoding format of a encoded video stream of the plurality of encoded video streams corresponds to a compression or encoding format that is identified to trigger a crash on a GPU of the at least one GPU and the CPU, to cause a skipping of one or more image frames of the encoded video stream of the plurality of encoded video streams with the compression or encoding format that is identified to trigger a crash of a GPU of the at least one GPU and the CPU. 16. A video decoding system for simultaneously decoding a plurality of encoded video streams of one or more video compression formats and displaying each resulting decoded video stream in a predetermined tile of a display, the system comprising: a data interface configured to receive said plurality of encoded video streams; a processing unit (CPU) in communication with the data interface; a display control device in communication with the CPU, the display control device comprising at least one graphical processing unit (GPU); a display in communication with the display control device; and memory storing an attribution module configured to direct each of the plurality of encoded video streams to be decoded by one of the CPU and the GPU, and to detect that a compression or encoding format of a encoded video stream of the plurality of encoded video streams corresponds to a compression or encoding format that is identified to trigger a crash on a GPU of the at least one GPU and the CPU, to cause a skipping of one or more image frames of the encoded video stream of the plurality of encoded video streams with the compression or encoding format that is identified to trigger a crash of a GPU of the at least one GPU and the CPU. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form 892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER D LE whose telephone number is (571)270-5382. The examiner can normally be reached on Monday - Alternate Friday: 10AM-6:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SATH PERUNGAVOOR can be reached on 571-272-7455. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER D LE/ Primary Examiner, Art Unit 2488
Read full office action

Prosecution Timeline

Dec 24, 2024
Application Filed
Mar 04, 2026
Non-Final Rejection — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
97%
With Interview (+16.9%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 613 resolved cases by this examiner. Grant probability derived from career allow rate.

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