DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/06/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7-8 are rejected under 35 U.S.C. 102(a)91) as being anticipated by Grootes et al. (Pub. No.: US 20070046485 A), hereafter Grootes.
Regarding claim 1, Grootes teaches an apparatus, comprising:
a control logic circuit having a configuration input, a pulse width modulation (PWM) input (Fig. 5 PWM control 50), a first control output (Fig. 4, PWM Control to Linear C/S, 40), a second control output (Fig. 4, PWM Control to Linear C/S, 41), and a third control output (Fig. 4, PWM Control to Linear C/S, 42), the configuration input configured to receive a configuration value indicative of a first status or a second status, the control logic configured to generate a first signal at the first control output indicative of the first status or the second status, a second signal at the second control output indicative of a first dimming status, and a third signal at the third control output indicative of a second dimming status (paragraph [0041], “Each current source 40-42 is controllable to control the brightness of its associated LEDs to achieve the desired white point. Each current source may be that shown in FIG. 1, 2, or 3, with control inputs being Vref (or Iset) and enable (EN). In FIG. 4. the Vref or Iset terminals are labeled AM (amplitude modulation), and the EN terminals are coupled to a PWM controller. Either the magnitude of AM or the duty cycle of EN may be used to control the brightness of the respective LEDs. The AM lead is used to control the "linear" conductivity of the pass transistor 14 when the current source is enabled by the signal EN” here first and second signals are “EN” signals and controlled brightness implies dimming status) ;
a switching converter controller (FIG. 4, SMPS Voltage Source 44, 45, 46) having a clock input (FIG. 4 VFB)); and
a clock circuit including an oscillator configured to generate an oscillator clock (paragraph [0049], “FIG. 5 illustrates any of the PWM controllers 50, connected to a PWM control line in FIG. 4, that receive a control signal to vary the duty cycle of an oscillator operating at a fixed frequency”) , the clock circuit having a first control input, a second control input, a third control input (FIG. 11, inputs to 116. 117 and 118), a clock output (FIG. 11, output of 116. 117 and 118), and a synchronization terminal, the clock output coupled to the clock input, the clock circuit configured to: in response to the first status, generate a first clock at the clock output based on a synchronization clock received at the synchronization terminal; and in response to the second status, generate the first clock at the clock output based on the oscillator clock and generate a synchronization clock at the synchronization terminal also based on the oscillator clock (paragraph [0064], “the user wants control over the overall brightness and white point of the backlight. A external PWM controller 114 is provided for each color of LEDs to vary the brightness of each serial string of LEDs. In this way, the RGB balance and overall brightness of the backlight may be adjusted by the user. In one embodiment, the external PWM controller 114 generates a blanking signal for each PWM controller 108-110 at a frequency that is the same as or higher than the switching frequency of the PWM controllers 108-110. AND gates 116-118 are used for blanking the PWM signals. The switching frequency of the external PWM controller 114 will typically be 1 to 128 times that of the frequency of the controllers 108-110. In one embodiment, the external PWM controller 114 generates a common clock for synchronizing all the controllers 108-110 and 114”).
Regarding claim 7, Grootes teaches an apparatus, comprising:
a control logic circuit having a configuration input, a pulse width modulation (PWM) input (Fig. 5 PWM control 50), a first control output (Fig. 4, PWM Control to Linear C/S, 40), a second control output (Fig. 4, PWM Control to Linear C/S, 41), and a third control output (Fig. 4, PWM Control to Linear C/S, 42), the configuration input configured to receive a configuration value indicative of a first status or a second status, the control logic configured to generate a first signal at the first control output indicative of the first status or the second status, a second signal at the second control output indicative of a first dimming status, and a third signal at the third control output indicative of a second dimming status (paragraph [0041], “Each current source 40-42 is controllable to control the brightness of its associated LEDs to achieve the desired white point. Each current source may be that shown in FIG. 1, 2, or 3, with control inputs being Vref (or Iset) and enable (EN). In FIG. 4. the Vref or Iset terminals are labeled AM (amplitude modulation), and the EN terminals are coupled to a PWM controller. Either the magnitude of AM or the duty cycle of EN may be used to control the brightness of the respective LEDs. The AM lead is used to control the "linear" conductivity of the pass transistor 14 when the current source is enabled by the signal EN” here first and second signals are “EN” signals and controlled brightness implies dimming status) ;
a clock circuit including an oscillator configured to generate an oscillator clock (paragraph [0049], “FIG. 5 illustrates any of the PWM controllers 50, connected to a PWM control line in FIG. 4, that receive a control signal to vary the duty cycle of an oscillator operating at a fixed frequency”) , the clock circuit having a first control input, a second control input, a third control input (FIG. 11, inputs to 116. 117 and 118), a clock output (FIG. 11, output of 116. 117 and 118), and a synchronization terminal, the clock output coupled to the clock input, the clock circuit configured to: in response to the first status, generate a first clock at the clock output based on a synchronization clock received at the synchronization terminal; and in response to the second status, generate the first clock at the clock output based on the oscillator clock and generate a synchronization clock at the synchronization terminal also based on the oscillator clock (paragraph [0064], “the user wants control over the overall brightness and white point of the backlight. A external PWM controller 114 is provided for each color of LEDs to vary the brightness of each serial string of LEDs. In this way, the RGB balance and overall brightness of the backlight may be adjusted by the user. In one embodiment, the external PWM controller 114 generates a blanking signal for each PWM controller 108-110 at a frequency that is the same as or higher than the switching frequency of the PWM controllers 108-110. AND gates 116-118 are used for blanking the PWM signals. The switching frequency of the external PWM controller 114 will typically be 1 to 128 times that of the frequency of the controllers 108-110. In one embodiment, the external PWM controller 114 generates a common clock for synchronizing all the controllers 108-110 and 114”) .
Regarding claim 8, Grootes further teaches a switching converter controller having a clock input, and wherein the clock output of the clock circuit is coupled to the clock input of the switching converter controller a switching converter controller (FIG. 4, SMPS Voltage Source 44, 45, 46 having a clock input (FIG. 4 VFB)).
Allowable Subject Matter
Claims 2-6, 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 1, comprising “the first one-shot circuit configured to generate an output pulse based on of a falling edge of the synchronization clock received at the synchronization terminal; and a second one-shot circuit having an input coupled to the oscillator, the second one-shot circuit configured to generate an output pulse based on a rising edge of the oscillator clock”, as required in combination with the other limitations of the claim.
Regarding claim 3, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 1, comprising “wherein the clock circuit includes a clock sample circuit having an input coupled to the synchronization terminal and having an output, the clock sample circuit configured to generate a flag to indicate whether the synchronization clock is present at the synchronization terminal”, as required in combination with the other limitations of the claim.
Regarding claim 4, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 1, comprising “the first switch terminal coupled to the error amplifier output; and a resistor coupled in series with a capacitor between the second switch terminal and a supply voltage terminal”, as required in combination with the other limitations of the claim.
Dependent claim 5 is also objected by virtue of its dependency.
Regarding claim 6, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 1, comprising “a power stage circuit having a power stage circuit terminal coupled to the switching terminal, the power stage circuit also having an output terminal; and an illumination device coupled to the output terminal”, as required in combination with the other limitations of the claim.
Regarding claim 6, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 1, comprising “a power stage circuit having a power stage circuit terminal coupled to the switching terminal, the power stage circuit also having an output terminal; and an illumination device coupled to the output terminal”, as required in combination with the other limitations of the claim.
Regarding claim 9, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 8, comprising “the first switch terminal coupled to the error amplifier output; and a resistor coupled in series with a capacitor between the second switch terminal and a supply voltage terminal”, as required in combination with the other limitations of the claim.
Regarding claim 10, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 8, comprising “a power stage circuit having a power stage circuit terminal coupled to the switching terminal, the power stage circuit also having an output terminal; and an illumination device coupled to the output terminal”, as required in combination with the other limitations of the claim.
Regarding claim 11, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 7, comprising “a first one-shot circuit having an input coupled to the synchronization terminal, the first one-shot circuit configured to generate an output pulse based on of a falling edge of the synchronization clock received at the synchronization terminal; and a second one-shot circuit having an input coupled to the oscillator, the second one-shot circuit configured to generate an output pulse based on a rising edge of the oscillator clock”, as required in combination with the other limitations of the claim.
Regarding claim 12, prior arts whether stand alone or in combination fail to teach or reasonably suggest the apparatus according to Claim 7, comprising “, the clock sample circuit configured to generate a flag at the output of the clock sample circuit to indicate whether the synchronization clock is present at the synchronization terminal”, as required in combination with the other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED M KAISER whose telephone number is (571)272-9612. The examiner can normally be reached M-F 9 a.m.-6 p.m..
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/SYED M KAISER/Examiner, Art Unit 2831 /ABDULLAH A RIYAMI/Supervisory Patent Examiner, Art Unit 2831
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