DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Election of Species Requirement
2. Applicant’s election of species C, corresponding to figures 3 and 4 and claims 1 and 5-11, is acknowledged. Claims 1 and 5-11 are now subject to examination on the merits and claims 2-4 and 12-18 are withdrawn from consideration. Although the election is with traverse, because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statements
3. The information disclosure statements (IDS) submitted on 12/24/24 and 04/15/26 have been considered by the examiner.
Priority
4. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
5. The disclosure is objected to because of the following informalities: on the first line of paragraph [0003], the word "which" should be changed to --, wherein the GPIO pin--, in order to clarify that it is the GPIO pin which can be programmed to act as either an input or an output. On line 4 of paragraph [0003], it appears that the word --pin-- should be inserted after "GPIO". On line 5 of paragraph [0004], it appears that --is driven-- should be inserted after the second occurrence of the word "transistor", and note that the same insertion should also be made on line 7 of this paragraph, again after the second occurrence of the word "transistor". On the first line of paragraph [0006], the word "relates" should be changed to --relate--. On line 3 of paragraph [0007], the word "an" should be changed to --each--. On the second line of paragraph [0016], the word "includes" should be changed to --include--, and on line 5 of this paragraph, the word "it" should be changed to --they--. On line 7 of paragraph [0016], --described as-- should be inserted after the second occurrence of the word "is", and on line 8 of this paragraph, the word "it" should be changed to -- this--. On line 15 of paragraph [0017], the comma after "mp1" should be deleted. On the last line of paragraph [0019], the word "inversed" should be changed to --inverted--. On line 3 of paragraph [0022], --mnon-- should be inserted after the word "transistor". On the first line of paragraph [0023], the word "includes" should be changed to --include--. On line 4 of paragraph [0025], it appears that "VA, VB or VC" should be changed to --VPa, VPb or VPc--, note what is illustrated in figure 5 of the instant drawings. On the first line of paragraph [0028], the word "provides" should be changed to --illustrates--, and on line 5 of this paragraph, --a-- should be inserted before the word "drain". On the last line of paragraph [0028], --a-- should again be inserted before the word "drain". On line 5 of paragraph [0029], the word "one" should be changed to --the--, and on line 6 of this paragraph, a comma should be inserted after the word "voltages". On line 3 of paragraph [0030], the word "inversed" should again be changed to --inverted--, and on the penultimate line of this paragraph, a comma should again be inserted after the word "voltages". On line 5 of paragraph [0031], the word "now" should be deleted, and also in this paragraph, on line 6 thereof, the word "then" should also be deleted. On line 8 of paragraph [0031], the word "now" should again be deleted, and also on this line, the word "voltage" should be changed to --volts--. On the first line of paragraph [0032], the word "Referencing" should be changed to --Referring--, and on line 5 of this paragraph, --a-- should be inserted before the word "source". On line 6 of paragraph [0032], the word --and-- should be inserted before "a". On line 3 of paragraph [0033], the word "reused" should be changed to --used--, and on line 4 of this paragraph, "a" should be changed to --an--. On line 5 of paragraph [0033], the word --time-- should be inserted after "which", and on line 8 of this paragraph, the word "meanwhile" should be changed to --and--. On line 9 of paragraph [0033], --to be-- should be inserted after the word "configured", and note that the same insertion should also be made on line 10 of this paragraph. On the first line of paragraph [0034], the word "Referencing" should again be changed to --Referring--. On line 10 of paragraph [0034], --to be-- should again be inserted after the word "configured", and note that the same insertion should also be made on line 12 of this paragraph. On line 7 of paragraph [0035], --a-- should be inserted before the word "drain".
Appropriate correction is required.
Drawings
6. The drawings are objected to because in instant figure 4, it appears that "gate_p" should be changed to --gate_2--, in view of what is indicated on line 5 of paragraph [0022]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
7. Claims 1 and 5-9 are objected to because of the following informalities:
On the first line of claim 1, the word --purpose-- should be inserted after "general".
On the penultimate line of claim 1, the word "and" at the beginning of the line should be deleted.
On the first line of claim 5, the word --wherein-- should be inserted after "1,".
On the first line of claim 6, the word --wherein-- should be inserted after "1,".
On line 14 of claim 7, the word "grounded" should be changed to --ground--.
On the first line of claim 8, a comma should be inserted after "1", and also on this line, the word "includes" should be changed to --including--.
On the first line of claim 9, the word "inversed" should be changed to --inverted--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
8. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5-11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
On the second line of claim 5, "a second gate drive circuit" lacks antecedent basis, the reason being that claim 5 goes back to claim 1, and no first gate drive circuit is recited anywhere in claim 1, i.e., it appears that claim 5 should actually depend from claim 2 where the first gate drive circuit is introduced.
On the second line of claim 6, "a second gate drive circuit" again lacks antecedent basis, for the same reason noted above in the rejection of claim 5. On lines 2-3 of claim 6, "a fourth NMOS transistor" lacks antecedent basis, the reason being that claim 6 goes back to claim 1, and no second or third NMOS transistors are recited anywhere in claim 1, i.e., it appears that claim 6 should actually depend from claim 3 where the second and third NMOS transistors are introduced. Note the same problem regarding the recitation of "a fifth NMOS transistor" on line 3 of claim 6.
On the second line of claim 7, "a second gate drive circuit" again lacks antecedent basis, for the same reason noted above in the rejections of claims 5 and 6, and note the same problem regarding the recitation of "a fourth NMOS transistor" and "a fifth NMOS transistor" recited on line 3 of claim 7, i.e., there is no antecedent basis for these recitations because claim 1 does not recite any second or third NMOS transistors.
On lines 2-3 of claim 8, "a seventh NMOS transistor", "a fourth PMOS transistor" and "a fifth PMOS transistor" all lack of antecedent basis, the reason being that claim 1 does not recite any second through sixth NMOS transistors, or a third PMOS transistor, or third or fourth PMOS transistors.
Claim 9 is indefinite in view of its dependency on indefinite claim 8.
On the first two lines of claim 10, "the maximum power supply voltage among the multiple power supply voltages within the chip" lacks antecedent basis, i.e., neither claim 1 nor claim 8 recite a maximum power supply voltage among the multiple power supply voltages within the chip.
On the first two lines of claim 11, "the maximum power supply voltage among the multiple power supply voltages within the chip" lacks antecedent basis, i.e., neither claim 1 nor claim 8 recites a maximum power supply voltage among the multiple power supply voltages within the chip.
Claim Rejections - 35 USC § 102
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gao et al, U.S. Patent Application Publication No. 2015/0098160.
As to caim 1, Gao et al discloses, in figure 2,
a general purpose input/output (GPIO) circuit having an output circuit, the output circuit comprising:
a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor (NMV1), coupled between a GPIO pin (GIPO pin labeled GateDriver_Output) and a reference ground (Vgnd);
a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor (PMV1) and a second PMOS transistor, coupled in series between an operating voltage output terminal (the terminal which receives operating voltage Vs) and the GPIO pin;
wherein the first NMOS transistor includes a source coupled to the reference ground, a drain coupled to the GPIO pin and a gate (note that the source of transistor NMV1 is coupled to reference ground Vgnd, and the drain of this transistor is coupled to pin GateDriver_Output);
the first PMOS transistor includes a drain coupled to the operating voltage output terminal, a gate and a source (note that the drain of transistor PMV1 is coupled to supply voltage Vs);
the second PMOS transistor includes a drain coupled to the GPIO pin, a gate and a source (note that the drain of transistor PMV2 is coupled to pin GateDriver_Output);
wherein the source of the first PMOS transistor is coupled to the source of the second PMOS transistor and forms a first common node (note that the source terminals of transistors PMV1 and PMV2 are coupled together at a first common node).
As to claim 5, the claimed second gate drive circuit reads on the combination of inverter circuit I1 and circuit 220 or, alternatively, either of these two circuit components by itself, and the functional limitations recited on lines 2-6 of claim 5 appear to be inherent during the operation of Gao et al's figure 2 general purpose input/output circuit, note that it has long been held by the courts that where the examiner has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, the examiner possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on, see In re Swinehart, 58 CCPA 1027, 169 USPQ 226 (1971).
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Gao et al, supra, in view of any one of Lin et al (USPAP 2026/0068010), Yasuda et al (USPAP 2019/0228295) and Hanagami et al (USPAP 2021/0288648).
Although Gao does not disclose a voltage selection circuit such as voltage selection circuit 500 shown in figure 5 of the instant drawings--where the voltage selection circuit is used for selecting a power supply voltage among multiple selectable power supply voltages within a chip for powering the first gate drive circuit--the use of such a voltage selection circuit would have been obvious to one of ordinary skill in the art, the reason being that it was old and well-known in the art before the effective filing date of applicant's invention that a gate drive circuit is typically powered by one of a plurality of selectable power supply voltages within a chip, three examples of this well-known concept being disclosed by Lin et al (note circuit 932 shown in figure 9 of this reference, wherein circuit 932 is a power supply selector circuit which selects one of a plurality of different level power supply voltages for use in powering driver circuit 934), Yasuda et al (note circuit 195 shown in figure 5 of this reference, wherein circuit 195 is a power supply selector circuit which selects one of a plurality of different level power supply voltages for use in powering driver circuit 40), and Hanagami et al (note circuit 220 shown in figure 2 of this reference, wherein circuit 220 is a power supply selector circuit which selects one of a plurality of different power supply voltages for use in powering driver circuits P5/N1 and B1). Applicant should note that the details of the voltage selection circuit recited in claims 8-10 were all old and well-known in the art before the effective filing date of applicant’s invention, and further note that there is motivation for the ordinarily skilled circuit designer to use such a power supply selector for selecting between different power supply voltages in the gate driver circuit shown in Gao et al's figure 2, i.e., to provide the obvious advantage of being able to control the amplitude of the gate drive signal applied to NMOS pulldown transistor NMV1.
Allowable Subject Matter
11. Claims 6, 7 and 11 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record discloses or suggests the GPIO circuit of claim 1 with the further limitations of a second gate drive circuit, a fourth NMOS transistor, a third PMOS transistor and a fifth NMOS transistor configured as recited in claim 6; nor does any of the prior art of record disclose or suggest the GPIO circuit of claim 1 with the further limitations of a fourth NMOS transistor, a third PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a pulse generator and a first current source configured as recited in claim 7; nor does any of the prior art of record disclose or suggest the GPIO circuit of claim 8 with the further limitations that the maximum power supply voltage among the multiple power supply voltages within the chip is assigned to the first power terminal and the remaining power supply voltages are assigned to the second power terminal, as recited in claim 11.
Prior Art Not Relied Upon
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Figure 3 of Ohta et al is also seen to anticipate at least independent claim 1, note NMOS transistor Q113 coupled between GPIO pin 102 and reference ground, and note also PMOS transistors Q111 and Q112 coupled in series with each other between operating voltage V and GPIO pin 102, where these two PMOS transistors have their source terminals connected together at a common node.
Figure 4 of Guo, figure 1 of Ou et al, figure 1 of Desel, figure 1 of Taylor, figure 3 of Liu et al and figure 9 of Otani et al show additional examples of first and second PMOS transistors connected in series with each other wherein the source terminals of the two transistors are coupled directly together, similar to what is disclosed by Gao et al, supra.
Figure 6 of Bhattacharya et al, figure 5 of Krishnan, figure 2b of Zid et al, and figure 5 of Shukh et al show for examples of a voltage selection circuit similar to applicant's voltage selection circuit 500 shown in figure 5 of the instant drawings, applicant should note that using a first amplifier circuit for generating the claimed first and second selection signals of claim 8 would have been obvious because it was old and well-known in the art before the effective filing date of applicant's invention to use such a first amplifier circuit for receiving a voltage selection signal and outputting first and second complementary selection signals based on such a voltage selection circuit, i.e., such is a well-known single-ended to differential amplifier.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH B WELLS/Primary Examiner, Art Unit 2836 June 1, 2026
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