DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d) which papers have been placed of record in the file.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is objected to because:
The Cross-Reference to Related Applications section in paragraph [0001] of the specification does not provide the status of U.S. application serial no. 18/164,402 (i.e., now U.S. Patent No. 12,197,279).
Drawings
The formal drawings are accepted.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites:
A memory fault handling method, wherein the method comprises:
receiving, a second fault repair request, wherein the second fault repair request requests to repair the memory, and wherein the second fault repair request comprises at least one of a fault feature mode of the memory or an isolation repair technology used to repair the memory; and repairing the memory based on the isolation repair technology or the fault feature mode.
As per claims 1 these claims recite “a second fault repair request”. It is unclear if there is a first fault repair request. Further, the claim recites “isolation repair technology”, is it isolating a faulty memory? And furthermore, what type of isolation is referring? A hardware isolation or a software isolation? In addition, is the fault repair request is received to select between the fault feature mode of the memory and an isolation repair technology and interconnections between one of a fault feature mode of the memory or an isolation repair technology is confusing and for the most part not detailed or mentioned in the claim. It is difficult to translate the claim and follow what processes are taking place. Over all the limitation attempts to define the subject matter in terms of the result to be achieved, which merely amounts to a statement of underlying problem, without providing the technical features necessary for achieving the result. Clarification is required.
Independent claims 9 and 17 include similar limitations of independent claim 1 andtherefore are rejected for similar reasons.
Dependent claims depend from the base claims and inherently include limitations therein and therefore are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as well.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,197,279.
For example, claim 1 of the present application teaches “A memory fault handling method, wherein the method comprises: receiving, a second fault repair request, wherein the second fault repair request requests to repair the memory, and wherein the second fault repair request comprises at least one of a fault feature mode of the memory or an isolation repair technology used to repair the memory; and repairing the memory based on the isolation repair technology or the fault feature mode. Whereas claim 1 of U.S. PN: 12,197,279 teaches “A memory fault handling method, comprising: obtaining, by a management module, error information of a memory in an electronic device, wherein the error information includes at least one of the error information of the memory comprises at least one of a state of a corrected error (CE), occurrence time of the CE, a quantity of CEs, physical address information of the CE, a state of an uncorrected error, occurrence time of the uncorrected error, a quantity of uncorrected errors, physical address information of the uncorrected error, a quantity of memory patrol errors, a row address of the memory patrol error, a column address of the memory patrol error, or a row address with a maximum quantity of memory patrol errors; determining, by the management module, based on the error information of the memory, a fault feature mode of the memory or an isolation repair technology to repair the memory, wherein the fault feature mode comprises at least one of a page fault mode, a single-bit bit fault mode, a cell fault mode, a row fault mode, a column fault mode, a bank fault mode, a device fault mode, a rank fault mode, a channel fault mode, a dual in-line memory module (DIMM) fault mode, a fault mode in which a quantity of continuous errors occur is under a first threshold, or a fault mode in which a quantity of errors over a second threshold occur in a short period of time, wherein the first threshold is lower than the second threshold; determining, by the management module, based on the fault feature mode of the memory or the isolation repair technology to repair the memory, to repair the memory using at least one of hardware isolation or software isolation; sending, by the management module, based on determining to repair the memory using hardware isolation, a first fault repair request to a processor firmware; and sending, by the management module, based on determining to repair the memory using software isolation, a second fault repair request an operating system (OS) management unit”.
Rationales:
The instant application is a broader version of claim 1 of U.S. Patent No. 12,197,279, and several limitations in patented claim 1 have removed from the instant application of claim 1. Thus, claim 1 of the instant application may be considered as defining a broader genus version of the species defined in claim 1 of U.S. Patent No. 12,197,279. Therefore, the claims are obvious variations of each other and not patentably distinct.
“A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Humans are a species of the animal genus. Our case law firmly establishes that a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim. In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 1053, 29 USPQ2d 2010, 2016(Fed. Cir. 1993); In re Gosteli, 872 F.2d 1008, 1010, 10 USPQ2d 1614, 1616(Fed. Cir. 1989); Titanium Metals Corp. v. Banner, 778 F.2d 775,782, 227 USPQ 773,779 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d at 944, 214 USPQ at 767 (C.C.P.A. 1982)." ELI LILLY AND COMPANY v BARB LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Other parallel independent claims of the instant application have corresponding issues with the independent claims of Patent No. 12,197,279 are also rejected under non-statutory obviousness-type double patenting for the same rationales discussed above.
Dependent claims are deemed obvious over the dependent claims of the '279 patent for the same rationales discussed above.
35. U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites:
A memory fault handling method, wherein the method comprises:
receiving, a second fault repair request, wherein the second fault repair request requests to repair the memory, and wherein the second fault repair request comprises at least one of a fault feature mode of the memory or an isolation repair technology used to repair the memory; and repairing the memory based on the isolation repair technology or the fault feature mode.
At step 1, the independent claim | recites a method of fault handling, and therefore is a process, which is a statutory category of invention.
At step 2A, prong one, the claim recites a memory fault handling method, wherein the method comprises: receiving, a second fault repair request, wherein the second fault repair request requests to repair the memory, and wherein the second fault repair request comprises at least one of a fault feature mode of the memory or an isolation repair technology used to repair the memory; and repairing the memory based on the isolation repair technology or the fault feature mode.
The limitation repairing a memory based on the isolation repair technology or the fault feature mode, as drafted, is a process that under its broadest reasonable interpretation, covers performance of the limitations in the mind. That is, nothing in the claim elements preclude the steps from practically being performed in the mind. For example, repairing a memory based on the isolation repair technology or the fault feature mode, as drafted, is a process in the context of this claim encompasses making a decision based on observations, evaluation or judgment of a value.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
At step 2A, prong two, this judicial exception is not integrated into a practical application. The claim recites the additional elements “receiving, a second fault repair request, wherein the second fault repair request requests to repair the memory; and wherein the second fault repair request comprises at least one of a fault feature mode of the memory or an isolation repair technology used to repair the memory.” The elements of receiving a second fault repair request…….and repairing the memory are not indicative of integration into a practical application because they amount to no more than generally linking the use of the exception to a particular field of use (MPEP 2106.05(h)). The steps of receiving a request or command to repair the memory are not indicative of integration into a practical application because they amount no more than extra-solution activity that is not directly linked to the abstract idea (MPEP 2106.05(g)). Even when viewed in combination, the additional elements in this claim do not do more than use mental processes making a decision (i.e. repair data) based on an observation, evaluation or judgment of a value.
Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
At step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the claim amount to no more than linking the abstract idea to a field of use and performing well-understood, routine and conventional extra-solution activities. Additionally, the element of “a memory” merely apply the exception using generic components, which cannot provide an inventive concept. Considering the additional element with the claim as a whole, the additional element does not provide significantly more than the abstract idea. The claim is not patent eligible.
Claim 9 recites a non-transitory computer-readable storage medium and a processor that performs the method of claim 1. The additional elements (a non-transitory computer-readable storage medium and a processor) perform the method of claim 1. As such the claimed invention recites an abstract idea. The additional elements (a non-transitory computer-readable storage medium and a processor) do not change the results of the analysis. At step 2A, non-transitory computer-readable storage medium and a processor figured to perform the method do not integrate the abstract idea into a practical application because the limitation amounts to more instructions to implement the abstract idea on a computer (MPEP 2106.05(f). At step 2B, the additional elements merely apply the exception using generic components, which cannot provide an inventive concept. Therefore, the additional elements do not provide significantly more than the abstract idea. The claim is not patent eligible.
Claim 17 recites a device comprising one or more processors; and at least one non-transitory computer readable memory connected to the one or more processors that performs the method of claim 1. The additional elements a (device comprising one or more processors; and at least one non-transitory computer readable memory connected to the one or more processors) perform the method of claim 1. As such the claimed invention recites an abstract idea. The additional elements (a device comprising one or more processors; and at least one non-transitory computer readable memory connected to the one or more processors) do not change the results of the analysis. At step 2A, a device comprising one or more processors; and at least one non-transitory computer readable memory connected to the one or more processors figured to perform the method do not integrate the abstract idea into a practical application because the limitation amounts to more instructions to implement the abstract idea on a computer (MPEP 2106.05(f). At step 2B, the additional elements merely apply the exception using generic components, which cannot provide an inventive concept. Therefore, the additional elements do not provide significantly more than the abstract idea. The claim is not patent eligible.
Dependent claims 2-10 are analyzed next to determine if they recite elements that add significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Liu et al. “herein after as Liu” (U.S. PN: 10,241,857) in view of Bell et al. “herein as Bell” (U.S. PN: 9,037,920).
As per claim 1, 9, and 17:
Liu substantially teaches or discloses a memory fault handling method (see abstract), wherein the method comprises: receiving, a second fault repair request, wherein the second fault repair request requests to repair the memory (see figures 2a, 2b and col. 2, lines 55-67 to col. 3, lines 1-9, col. 6, lines 43-67 to col. 7, lines 1-53);
Liu substantially teaches the claimed invention described in claim 1 (as indicated above).
However, Liu does not explicitly teach the fault repair comprises at least one of a fault feature mode of the memory or an isolation repair technology used to repair the memory; and repairing the memory based on the isolation repair technology or the fault feature mode.
Bell, in an analogous art, teaches that the fault repair request comprises at least one of a fault feature mode of the memory or an isolation repair technology used to repair the memory; and repairing the memory based on the isolation repair technology or the fault feature mode “the Rank Module 243, can be configured to calculate the likelihood that certain failure modes may be present, the likelihood that certain repairs may be needed to correct the fault, the benefit of collecting additional symptoms, and the cost/benefit ratio of performing additional tests to isolate the failure mode or repair. In other embodiments, the Rank Module 243, can be configured to produce a data summary that represents partial diagnostic conclusions determined at a node (120-160) for use by higher layer computing nodes. When invoked by the Workflow Service 310, the Rank Module 243 may examine each fault condition that contains updated or new symptoms in a "Symptoms of Interest" list. For each of the qualifying fault conditions in the list, statistical analysis methods available in the common utilities or elsewhere in the framework services may be used to calculate the following: 1. For each failure mode associated with the symptoms, the likelihood that the failure mode is present. 2. For each corrective action associated with the failure modes, the likelihood that the Corrective Action will fix the fault” (see col. 10, lines 47-67).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Liu with the teachings of Bell by including
a fault feature mode of the memory or an isolation repair technology used to repair the memory.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that using a fault feature mode of the memory or an isolation repair technology would have provided reduction in power consumption and increase in fault repairing operation.
Regarding claims 2, 10, and 18, the combination of Liu and Bell discloses the claimed invention discussed in claim 1. Bell teaches wherein the fault feature mode comprises at least one of a page fault mode, a single-bit bit fault mode, a cell fault mode, a row fault mode, a column fault mode, a bank fault mode, a device fault mode, a rank fault mode, a channel fault mode, a dual in-line memory module (DIMM) fault mode, a fault mode in which a small quantity of continuous errors occur, or a fault mode in which a large quantity of errors occur in a short period of time (see col. 10, lines 31-67 and col. 11, lines 1-6).
Regarding claims 3 and 11, the combination of Liu and Bell discloses the claimed invention discussed in claim 1. Lee teaches sending a second fault repair response, wherein the second fault repair response carries a repair result obtained after the memory is repaired (see col. 2, lines 55-67 to col. 3, lines 1-9).
Regarding claims 4 and 12, the combination of Liu and Bell discloses the claimed invention discussed in claim 1. Lee teaches wherein the method further comprises: receiving a second fault repair information table, wherein the second fault repair information table indicates at least one fault feature mode and one or more software isolation repair technologies corresponding to the at least one fault feature mode (see col. 7, lines 5-31 and col. 8, lines 18-67 to col. 9, lines 1-18).
Regarding claims 5, 13, and 20, the combination of Liu and Bell discloses the claimed invention discussed in claim 1. Bell teaches wherein the one or more software isolation repair technologies comprise at least one of page offline, address isolation, process isolation, or a software isolation repair technology for replacing a specific address range of the memory (see col. 10, lines 47-67).
Regarding claims 6 and 14, the combination of Liu and Bell discloses the claimed invention discussed in claim 1. Lee teaches wherein the method further comprises: determining, based on the fault feature mode of the memory and the second fault repair information table, an isolation repair technology to repair the memory (see col. 7, lines 5-31 and col. 8, lines 18-67 to col. 9, lines 1-18).
Regarding claims 7 and 15, the combination of Liu and Bell discloses the claimed invention discussed in claim 1. Lee teaches wherein the second repair fault request and second fault repair information table are received by a system management unit built in an operating system (OS) or a device management agent program installed in an OS (see col. 7, lines 5-31 and col. 8, lines 18-67 to col. 9, lines 1-18).
Regarding claims 8 and 16, the combination of Liu and Bell discloses the claimed invention discussed in claim 1. Lee teaches wherein the second repair fault request and second fault repair information table are sent by a management unit of a non-service module, and the management unit comprises one of a management unit for a running status, a management unit built in a processor, a management system in a management chip outside the processor, a server baseboard management controller (BMC), a system management module (SMM), or a device management system in the OS an operating system (OS) (see col. 16, lines 30-45).
Regarding claim 19, the combination of Liu and Bell discloses the claimed invention discussed in claim 1. Lee teaches wherein the computer program code further comprises computer program code for: sending a second fault repair response, wherein the second fault repair response carries a repair result obtained after the memory is repaired; and receiving a second fault repair information table, wherein the second fault repair information table indicates at least one fault feature mode and one or more software isolation repair technologies corresponding to the at least one fault feature mode; and determining, based on the fault feature mode of the memory and the second fault repair information table, the isolation repair technology to repair the memory (see col. 7, lines 5-31 and col. 8, lines 18-67 to col. 9, lines 1-18).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (U.S. PN: 10,776,227) describe a memory management method which repairs faults in a physical region and a virtual region using different spare cells, by means of an analyzing device. The method includes: repairing a fault by replacing a fault address with an address of a spare row in the physical region, by means of the analyzing device; and repairing a fault by replacing a fault address with an address of a spare column in the virtual region, by means of the analyzing device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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/ESAW T ABRAHAM/
Primary Examiner,
Art Unit 2112
Prosecution Insights