DETAILED ACTION
Claims 1 and 3-22 are present for examination.
Claims 1 and 21-22 have been amended.
Claim 2 has been canceled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sheaffer (US2012/0047344) in view of Bradford et al. (US 2019/0042248).
With respect to claim 1, Sheaffer teaches accessing a memory array (see Fig.1 and paragraph 18; memory array 155), wherein the memory array includes a plurality of memory banks (see Fig. 1, paragraph 18; data is read from multiple banks), and wherein each column in the memory array is associated with a unique memory bank within the plurality of memory banks (see paragraph 19; each memory row is divided into four banks (e.g., columns 151-154));
receiving a request to transpose a matrix (see paragraphs 18 and 28; permutation operations are rotate operations, for example to perform a matrix transpose operation), wherein the matrix comprises i rows (see paragraph 18-19 and 28; rows 110-140) and j columns (see paragraph 18-19 and 28; columns 151-154);
saving, in the memory array, the matrix (see paragraph 29; a loading instruction on table 171), wherein the saving includes rotating, to the right, each row within the i rows (see paragraph 31-33; rotate data elements from the second row of table 171 to the right by 4 bytes; load the result of the rotation to row 120); and
reading, from the memory array (see paragraph 34; a reading instruction), the diagonal format of the matrix (see paragraphs 35-38; B4, C4, D4, and A4, are read from 4 different banks), wherein the reading includes rotating, to the left, each row within the diagonal format of the matrix (see paragraph 36-38; D2, A2, B2, and C2 are read from 4 different banks and become data 163; data 163 are rotated to the left for 4 bytes (one data element) and become A2, B2, C2, D2 at outgoing data 164), and wherein the reading produces a transpose of the matrix (see paragraph 18; re-ordering apparatus reads data from multiple banks of memory array 155 and permutes the data (e.g., data 163) to produce outgoing data (e.g., data 164). In one embodiment, the permutation operations are rotate operations, for example to perform a matrix transpose operation).
Sheaffer does not explicitly teach wherein the rotating is based on a row index, and wherein the saving results in a diagonal format of the matrix within the memory array, wherein the rotating aligns each element within each row of the matrix with a unique memory bank in the plurality of memory banks.
However, Bradford et al. teaches wherein for each buffered row X of the specified source matrix; cause the row to be written to the load buffer in a diagonal (i.e., matric is stored in diagonal format), starting at a matrix location shifted left by X positions… and executing, by the execution circuitry, a second operation to rotate each row Y of the reorder buffer rightwards by Y positions (i.e., rotation is done based on row index) (see paragraphs 58-60 and 215); and using a load rotator to rotate each row by X elements, thereby lining up each element with the column of the load buffer in which it will be written (see paragraphs 35, 55 and 59).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer to include the above mentioned to efficiently execute a matrix transpose instruction with significant speedup and to improve performance by allowing each element of the load rotator to be broadcasted along a single column of the load buffer (see Bradford, paragraphs 36 and 59).
With respect to claim 3, Sheaffer teaches wherein the saving is accomplished within a single cycle of the memory array (see paragraph 34; in one clock cycle, a data element from one bank (from each memory row) is driven onto the corresponding output ban.
With respect to claim 4, Sheaffer teaches wherein the reading is accomplished within a single cycle of the memory array (see paragraph 39; operations 5-8 is performed in a clock cycle each).
With respect to claim 21, Sheaffer teaches a computer program product embodied in a non-transitory computer readable medium for data processing, the computer program product comprising code which causes one or more processors to generate semiconductor logic for (see paragraph 13; apparatuses may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium):
accessing a memory array (see Fig.1 and paragraph 18; memory array 155), wherein the memory array includes a plurality of memory banks (see Fig. 1, paragraph 18; data is read from multiple banks), and wherein each column in the memory array is associated with a unique memory bank within the plurality of memory banks (see paragraph 19; each memory row is divided into four banks (e.g., columns 151-154));
receiving a request to transpose a matrix (see paragraphs 18 and 28; permutation operations are rotate operations, for example to perform a matrix transpose operation), wherein the matrix comprises i rows (see paragraph 18-19 and 28; rows 110-140) and j columns (see paragraph 18-19 and 28; columns 151-154);
saving, in the memory array, the matrix (see paragraph 29; a loading instruction on table 171), wherein the saving includes rotating, to the right, each row within the i rows (see paragraph 31-33; rotate data elements from the second row of table 171 to the right by 4 bytes; load the result of the rotation to row 120); and
reading, from the memory array (see paragraph 34; a reading instruction), the diagonal format of the matrix (see paragraphs 35-38; B4, C4, D4, and A4, are read from 4 different banks), wherein the reading includes rotating, to the left, each row within the diagonal format of the matrix (see paragraph 36-38; D2, A2, B2, and C2 are read from 4 different banks and become data 163; data 163 are rotated to the left for 4 bytes (one data element) and become A2, B2, C2, D2 at outgoing data 164), and wherein the reading produces a transpose of the matrix (see paragraph 18; re-ordering apparatus reads data from multiple banks of memory array 155 and permutes the data (e.g., data 163) to produce outgoing data (e.g., data 164). In one embodiment, the permutation operations are rotate operations, for example to perform a matrix transpose operation).
Sheaffer does not explicitly teach wherein the rotating is based on a row index, and wherein the saving results in a diagonal format of the matrix within the memory array, wherein the rotating aligns each element within each row of the matrix with a unique memory bank in the plurality of memory banks.
However, Bradford et al. teaches wherein for each buffered row X of the specified source matrix; cause the row to be written to the load buffer in a diagonal (i.e., matric is stored in diagonal format), starting at a matrix location shifted left by X positions… and executing, by the execution circuitry, a second operation to rotate each row Y of the reorder buffer rightwards by Y positions (i.e., rotation is done based on row index) (see paragraphs 58-60 and 215); ); and using a load rotator to rotate each row by X elements, thereby lining up each element with the column of the load buffer in which it will be written (see paragraphs 35, 55 and 59).
.
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the program product taught by Sheaffer to include the above mentioned to efficiently execute a matrix transpose instruction with significant speedup and to improve performance by allowing each element of the load rotator to be broadcasted along a single column of the load buffer (see Bradford, paragraphs 36 and 59).
With respect to claim 22, Sheaffer teaches a memory which stores instructions (see Fig. 3 and paragraphs 13 and 45; computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, DVD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs));
one or more processors coupled to the memory wherein the one or more processors (see Fig. 3 and paragraph 45; processor 705 coupled to memories), when executing the instructions which are stored (see paragraphs 13 and 45; apparatuses may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium), are configured to:
access a memory array (see Fig.1 and paragraph 18; memory array 155), wherein the memory array includes a plurality of memory banks (see Fig. 1, paragraph 18; data is read from multiple banks), and wherein each column in the memory array is associated with a unique memory bank within the plurality of memory banks (see paragraph 19; each memory row is divided into four banks (e.g., columns 151-154));
receive a request to transpose a matrix (see paragraphs 18 and 28; permutation operations are rotate operations, for example to perform a matrix transpose operation), wherein the matrix comprises i rows (see paragraph 18-19 and 28; rows 110-140) and j columns (see paragraph 18-19 and 28; columns 151-154);
save, in the memory array, the matrix (see paragraph 29; a loading instruction on table 171), wherein the saving includes rotating, to the right, each row within the i rows (see paragraph 31-33; rotate data elements from the second row of table 171 to the right by 4 bytes; load the result of the rotation to row 120); and
read, from the memory array (see paragraph 34; a reading instruction), the diagonal format of the matrix (see paragraphs 35-38; B4, C4, D4, and A4, are read from 4 different banks), wherein the reading includes rotating, to the left, each row within the diagonal format of the matrix (see paragraph 36-38; D2, A2, B2, and C2 are read from 4 different banks and become data 163; data 163 are rotated to the left for 4 bytes (one data element) and become A2, B2, C2, D2 at outgoing data 164), and wherein the reading produces a transpose of the matrix (see paragraph 18; re-ordering apparatus reads data from multiple banks of memory array 155 and permutes the data (e.g., data 163) to produce outgoing data (e.g., data 164). In one embodiment, the permutation operations are rotate operations, for example to perform a matrix transpose operation).
Sheaffer does not explicitly teach wherein the rotating is based on a row index, and wherein the saving results in a diagonal format of the matrix within the memory array wherein the rotating aligns each element within each row of the matrix with a unique memory bank in the plurality of memory banks.
However, Bradford et al. teaches wherein for each buffered row X of the specified source matrix; cause the row to be written to the load buffer in a diagonal (i.e., matric is stored in diagonal format), starting at a matrix location shifted left by X positions… and executing, by the execution circuitry, a second operation to rotate each row Y of the reorder buffer rightwards by Y positions (i.e., rotation is done based on row index) (see paragraphs 58-60 and 215); ); and using a load rotator to rotate each row by X elements, thereby lining up each element with the column of the load buffer in which it will be written (see paragraphs 35, 55 and 59).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Sheaffer to include the above mentioned to efficiently execute a matrix transpose instruction with significant speedup and to improve performance by allowing each element of the load rotator to be broadcasted along a single column of the load buffer (see Bradford, paragraphs 36 and 59).
Claim(s) 5-6, 9-11 and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sheaffer (US2012/0047344) in view of Bradford et al. (US 2019/0042248) as applied to claim 1 above, and further in view of Guerrero (US 2006/0190517).
With respect to claim 5, Sheaffer and Bradford et al. do not teach wherein the memory array stores two or more matrices.
However, Guerrero teaches wherein the memory array stores two or more matrices (see paragraphs 33-34; memory element 102-1 may arrange media information as a two-dimensional (2D) matrix or array having N rows and M columns… media information may be arranged as one or more matrices).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 6, Sheaffer and Bradford et al. do not teach wherein the receiving includes a second matrix.
However, Guerrero teaches wherein the receiving includes a second matrix (see paragraph 41; media processing node 102 may transpose one or more matrices of information).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 9, Sheaffer and Bradford et al. do not teach wherein the accessing includes a second memory array.
However, Guerrero teaches wherein the accessing includes a second memory array (see paragraph 34; memory element 102-1 may arrange media information as a two-dimensional (2D) matrix or array having N rows and M columns… media information may be arranged as one or more matrices. Also in paragraph 51; an original matrix may be written on a per row basis and read on a per column basis to transpose data. A subsequent matrix may be written on a per column basis and read on a per row basis to transpose data).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 10, Sheaffer and Bradford et al. do not teach wherein the receiving includes a second matrix
However, Guerrero teaches wherein the receiving includes a second matrix (see paragraph 41; media processing node 102 may transpose one or more matrices of information in order to optimize storage of media information).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 11, Sheaffer and Bradford et al. do not teach wherein the request includes alternating between the memory array and the second memory array.
However, Guerrero teaches wherein the request includes alternating between the memory array and the second memory array (see paragraph 51; an original matrix may be written on a per row basis and read on a per column basis to transpose data. A subsequent matrix may be written on a per column basis and read on a per row basis to transpose data).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 13, Sheaffer and Bradford et al. do not teach dividing the matrix into at least two submatrices.
However, Guerrero teaches dividing the matrix into at least two submatrices (see paragraph 34; media information may be arranged as one or more matrices. Each matrix may, in turn, comprise multiple sub-matrices).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 14, Sheaffer and Bradford et al. do not teach wherein the saving and the reading include a first submatrix within the at least two submatrices.
However, Guerrero teaches wherein the saving and the reading include a first submatrix within the at least two submatrices (see paragraphs 53-54; transposing media information 200 may comprise transposing one or more sub-matrices 250).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 15, Sheaffer and Bradford et al. do not teach wherein the saving and the reading produce a transpose of the first submatrix.
However, Guerrero teaches wherein the saving and the reading produce a transpose of the first submatrix (see paragraphs 53-54; transposing media information 200 may comprise transposing one or more sub-matrices 250).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 16, Sheaffer and Bradford et al. do not teach wherein the saving and the reading include a second submatrix within the one or more submatrices.
However, Guerrero teaches wherein the saving and the reading include a second submatrix within the one or more submatrices (see paragraphs 53-54; transposing media information 200 may comprise transposing one or more sub-matrices 250).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 17, Sheaffer and Bradford et al. do not teach wherein the saving and the reading produce a transpose of the second submatrix.
However, Guerrero teaches However, Guerrero teaches wherein the saving and the reading produce a transpose of the first submatrix (see paragraphs 53-54; transposing media information 200 may comprise transposing one or more sub-matrices 250).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 18, Sheaffer and Bradford et al. do not teach assembling the transpose of the first submatrix and the transpose of the second submatrix, wherein the assembling comprises a transpose of the matrix.
However, Guerrero teaches assembling the transpose of the first submatrix and the transpose of the second submatrix, wherein the assembling comprises a transpose of the matrix (see paragraph 54; individually transposing one or more sub-matrices 250 may effectuate the transposition of an overall matrix).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer and Bradford et al. to include the above mentioned to optimize storage of information (see Guerrero, paragraph 41).
With respect to claim 19, Sheaffer teaches wherein the memory array comprises at least i columns (see paragraph 18-19 and 28; columns 151-154).
With respect to claim 20, Sheaffer teaches wherein the memory array comprises at least j rows (see paragraph 18-19 and 28; rows 110-140).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sheaffer (US2012/0047344), Bradford et al. (US 2019/0042248) and Guerrero (US 2006/0190517) as applied to claims 1 and 5-6 above, and further in view of Van Hook et al. (US 5,812,147).
With respect to claim 7, Sheaffer, Bradford et al. and Guerrero do not teach wherein the saving and the reading include a base address.
However, Van Hook et al. teaches wherein a base field of the instruction are added to an offset field to generate an effective byte address, addr, in memory 102. The contents of the base register represent a byte address in memory 102. Offset is an index based on the size of the data item to be moved and, in one embodiment, is required to be properly weighted before adding to the contents of the base register. If the data item to be moved is not a single byte, offset is then shifted left 1, 2, 3, or 4 bit positions to achieve the proper weighting. The data item starting at the effective byte address (addr) in memory 102 is loaded into the vector register specified by the vt field. A read from data RAM 102 accesses two double word elements, address and adress+8 (see column 5, lines 18-40).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer, Bradford et al. and Guerrero to include the above mentioned to efficiently move data to memory (see Van Hook, column 3, lines 41-46).
With respect to claim 8, Sheaffer, Bradford et al. and Guerrero do not teach indexing, by the base address, between the matrix and the second matrix stored in the memory array.
However, Van Hook et al. teaches wherein a base field of the instruction are added to an offset field to generate an effective byte address, addr, in memory 102. Offset is an index based on the size of the data item to be moved and, in one embodiment, is required to be properly weighted before adding to the contents of the base register... The data item starting at the effective byte address (addr) in memory 102 is loaded into the vector register specified by the vt field. A read from data RAM 102 accesses two double word elements, address and adress+8 (see column 5, lines 18-40 and column 24, lines 9-33).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer, Bradford et al. and Guerrero to include the above mentioned to efficiently move data to memory (see Van Hook, column 3, lines 41-46).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sheaffer (US2012/0047344), Bradford et al. (US 2019/0042248) and Guerrero (US 2006/0190517) as applied to claims 1 and 9-11 above, and further in view of Tran et al. (US2021/0191720).
With respect to claim 12, Sheaffer, Bradford et al. and Guerrero do not teach wherein the memory array and the second memory array comprise a streaming matrix transposer.
However, Tran et al. teaches a streaming matrix transposer (see paragraph 189; streaming engine 125 can transpose data elements at a different granularity).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Sheaffer, Bradford et al. and Guerrero to include the above mentioned because transposed streams avoid the cost of explicitly transforming the data in memory (see Tran, paragraph 144).
Response to Arguments
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
Applicant’s representative argues, on page 12, that Bradford et al. (US 2019/0042248) does not teach wherein the rotating aligns each element within each row of the matrix with a unique memory bank in the plurality of memory banks as recited in claims 1 and 21-22. Applicant’s representative argues that Bradford et al. does not teach the claim limitation because the diagonal write, taught by Bradford et al., is an address manipulation not a data rotation.
In response: The examiner disagrees. Bradford et al. teaches performing an efficient transposition by rotating the source data and writing into multiple entries of the load buffer (see paragraphs 35, 55 and 217)… execution circuitry 110 in some embodiments includes load rotator 112, which in some embodiments is a barrel shifter to align misaligned load data (see paragraph 39); and using a load rotator to rotate each row by X elements, thereby lining up each element with the column of the load buffer in which it will be written (see paragraph 59). Bradfort et al. teaches data rotation, to align the data received, and the writing of the rotated data into load buffer.
Applicant’s representative argues, on page 12, that Bradford et al. (US 2019/0042248) does not teach wherein the rotating aligns each element within each row of the matrix with a unique memory bank in the plurality of memory banks as recited in claims 1 and 21-22. Applicant’s representative argues that Bradford et al. does not teach the claim limitation because Bradford uses a load rotator, shifting the matrix location left by X positions, to prepare for writing the matrix location diagonally to the load buffer, which is not the same as a memory array.
In response: The examiner disagrees. Bradford et al. teaches wherein the execution of the MATRIXTRANSPOSE instruction causes the rows of a source matrix to be written as the columns of a destination matrix (see paragraph 34); and wherein transposing the specified source matrix is conducted in two steps: first, load rotator is used to copy elements into the correct row, and second, shuffle network 116 is used to rotate the elements into the correct column, then, the contents of the load buffer 114 are copied to the specified destination matrix 108 (see paragraph 40). Bradford et al. also teaches wherein a matrix may be stored in locations in memory, or in other storage accessible to execution circuitry (see paragraph 38); and wherein destination matrix 705 specifies memory locations to which to write execution results (see paragraph 86). Bradfort et al. does not only write the shifted elements to the load buffer; it teaches also teaches that after shifting is performed, the results are first written into the load buffer and then copied to the destination matrix (i.e., memory locations to which to write execution results).
Applicant’s representative argues, on page 12, that Guerrero (US 2006/0190517) does not teach wherein the rotating aligns each element within each row of the matrix with a unique memory bank in the plurality of memory banks as recited in claims 1 and 21-22.
In response: The examiner cited Bradford et al. (US 2019/0042248) to teach the above limitation. See the above response to arguments.
Applicant’s representative argues, on page 12, that Van Hook et al. (US 5,812,147) does not teach wherein the rotating aligns each element within each row of the matrix with a unique memory bank in the plurality of memory banks as recited in claims 1 and 21-22.
In response: The examiner cited Bradford et al. (US 2019/0042248) to teach the above limitation. See the above response to arguments.
Applicant’s representative argues, on page 12, that Tran et al. (US2021/0191720) does not teach wherein the rotating aligns each element within each row of the matrix with a unique memory bank in the plurality of memory banks as recited in claims 1 and 21-22.
In response: The examiner cited Bradford et al. (US 2019/0042248) to teach the above limitation. See the above response to arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hanounik et al. (US 2003/0084081) teaches transposing a two-dimensional array.
Ross (US 9,952,831) teaches transposing in a matrix-vector processor.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARACELIS RUIZ/ Primary Examiner, Art Unit 2139
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