Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is response to the Applicant’s Response to the Requirement for Election/Restriction in which the Applicant elected claims 21-32 for prosecution and non-elected claims 33-40. In the interview summary of 2/25/2026 as attached, the election was clarified as one without traverse..
Claims 21-40 are pending in which claims 21-32 stand rejected, objected to and claims 33-40 are non-elected. Claims 21 and 33 are independent claims.
Foreign Priority
Applicant’s claim for the benefit of a prior-filed CHINA Patent Applications CHINA 202311815527.5 filed 12/25/2023 and CHINA 202410066648.2 filed 01/16/2024, under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Claim Objections
Claims 21-40 are objected to because of the following informalities:
The claims are presented in the format [Claim #].
Patent claims must follow specific formatting rules to be considered valid and definite and the rules include that the Claims must be numbered consecutively in Arabic numerals (e.g., "1. A device...", "2. The device of claim 1...").
Accordingly, [Claim 21] should be Claim 21. ending with a period “.”, for example.
Further, [Claims 1-20] should be Claims 1-20 without ending with a period “.”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of - 35 USC § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 21, 24, 27, 30 and 32 are rejected under 35 USC § 103 as being unpatentable over
YAMADA et al.: "TERMINAL DEVICE, DATABASE SERVER, AND CALCULATION SYSTEM" (WIPO Patent Application Publication WO 2016129390 A1, DATE PUBLISHED 2016-08-18; and DATE FILED 2016-01-27, hereafter "YAMADA") in view of
White et al.: "METHODS FOR VERIFYING VECTOR DATABASE QUERY RESULTS AND DEVICES THEREOF" (United States Patent US 11947525 B1, DATE PUBLISHED 2024-04-02; and DATE FILED 2023-11-10, hereafter "White").
As per claim 21, YAMADA teaches a vector database, comprising:
an input for inputting a query vector (See Page 5, lines 3-5, The query device 103 transmits a query (for example, a query vector including elements of a plurality of query data) to the database server).
YAMADA does not explicitly teach a plurality of storage-processing units (SPU's), each SPU of said plurality of SPU's comprising at least a storage array for storing at least a data vector of said vector database, and a vector-distance calculation circuit (VDCC) for calculating a vector distance between said query vector and said data vector.
However, White teaches a plurality of storage-processing units (SPU's), each SPU of said plurality of SPU's comprising at least a storage array for storing at least a data vector of said vector database, and a vector-distance calculation circuit (VDCC) for calculating a vector distance between said query vector and said data vector(See col. 5, lines 23-29 and col. 8, lines 19-24, a variety of different types of memory storage devices, such as random-access memory (RAM), read only memory (ROM), hard disk, solid state drives, flash memory, or other reading and writing system that is coupled to the CPU(s) 300 and/or GPU(s) 302 can be used for the memory 304; the querier (e.g., the verifier device) sends a query vector q and the vector database 112 returns the data vector or row that has the lowest distance from q. An exact nearest neighbor (ENN) search necessarily gives the closest result, while for example an approximate nearest neighbor (ANN) search gives something that is approximately, but not necessarily exactly, the closest result. Here the storage that is coupled to the CPU(s) 300 and/or GPU(s) 302 suggests SPU coupled to CPU and GPU for efficiently and independently querying vector to and retrieving vector from a vector database and the vector database reads on a vector-distance calculation circuit (VDCC) for calculating the vector distance ).
It would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to combine White’s teaching with YAMADA because YAMADA is dedicated to a database server, a query device, a database system, a calculation system, and White is dedicated to verifying outsourced vector database query results to mitigate tampering of the stored underlying data and the execution of a query and a combined teaching would have improved YAMADA’s performance by surrogating storage management to storage processing unit(s) and focusing on heavy calculation tasks related to vectors.
YAMADA in view of White further teaches the following:
a minimum-distance search circuit (MDSC) communicatively coupled with said plurality of SPU's (See White: col. 8, lines 19-24, the querier (e.g., the verifier device) sends a query vector q and the vector database 112 returns the data vector or row that has the lowest distance from q. An exact nearest neighbor (ENN) search necessarily gives the closest result, while for example an approximate nearest neighbor (ANN) search gives something that is approximately, but not necessarily exactly, the closest result. Here the verifier device reads on the MDSC),
wherein said MDSC receives vector distances calculated by all VDCC's at said plurality of SPU's and searches for at least a minimum vector distance from said vector distances (See White: col. 8, lines 19-24, the querier (e.g., the verifier device) sends a query vector q and the vector database 112 returns the data vector or row that has the lowest distance from q. An exact nearest neighbor (ENN) search necessarily gives the closest result, while for example an approximate nearest neighbor (ANN) search gives something that is approximately, but not necessarily exactly, the closest result. Here the verifier device reads on the MDSC).
As per claim 24, YAMADA in view of White teaches the vector database according to claim 21, wherein said VDCC is configured to perform arithmetic operations on said query vector and said data vector (See White: col. 8, lines 19-24, the querier (e.g., the verifier device) sends a query vector q and the vector database 112 returns the data vector or row that has the lowest distance from q. An exact nearest neighbor (ENN) search necessarily gives the closest result, while for example an approximate nearest neighbor (ANN) search gives something that is approximately, but not necessarily exactly, the closest result.).
As per claim 27, YAMADA in view of White teaches the vector database according to claim 21, wherein said all VDCC's are configured to implement a same vector-distance calculating algorithm (See White: col. 8, lines 19-24, the querier (e.g., the verifier device) sends a query vector q and the vector database 112 returns the data vector or row that has the lowest distance from q. An exact nearest neighbor (ENN) search necessarily gives the closest result, while for example an approximate nearest neighbor (ANN) search gives something that is approximately, but not necessarily exactly, the closest result. Here the verifier device reads on the MDSC).
As per claim 30, YAMADA in view of White teaches the vector database according to claim 21, wherein said MDSC searches for at least a second minimum vector distance larger than said minimum vector distance (See White: col. 8, lines 19-24, the querier (e.g., the verifier device) sends a query vector q and the vector database 112 returns the data vector or row that has the lowest distance from q. An exact nearest neighbor (ENN) search necessarily gives the closest result, while for example an approximate nearest neighbor (ANN) search gives something that is approximately, but not necessarily exactly, the closest result.).
As per claim 32, YAMADA in view of White teaches the vector database according to claim 21, wherein said storage array is a random-access memory (RAM) array, a read-only memory (ROM) array, a non-volatile memory (NVM) array, or a three-dimensional memory (3D-M) array (See White: col. 5, lines 23-28, A variety of different types of memory storage devices, such as RAM, ROM, hard disk, solid state drives, flash memory, or 25 other computer-readable medium which is read from and written to by a magnetic, optical, or other reading and writing system).
Claims 22-23 are rejected under 35 USC § 103 as being unpatentable over
YAMADA in view of White, as applied to Claims 21, 24, 27, 30 and 32 above, and further in view of
APPU et al.: "BARRIERS AND SYNCHRONIZATION FOR MACHINE LEARNING AT AUTONOMOUS MACHINES" (TAIWAN Patent Application Publication TW 107108414 A, DATE PUBLISHED 2022-04-11; and DATE FILED 2018-03-13, hereafter "APPU").
As per claim 22, YAMADA in view of White does not explicitly teach said all VDCC's are parallel circuits configured to compute at said plurality of SPU's in parallel.
However, APPU teaches the vector database according to claim 21, wherein:
said all VDCC's are parallel circuits configured to compute at said plurality of SPU's in parallel (See Page 10, when parallel processing units 202 are used for graphics processing, scheduler 210 can be configured to divide the processing workload into approximately equally sized tasks to better enable distribution of graphics processing operations to processing clusters A plurality of clusters 214A- 214N of array 212).
It would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to combine White’s teaching with YAMADA in view of White because YAMADA is dedicated to a database server, a query device, a database system, a calculation system, White is dedicated to verifying outsourced vector database query results to mitigate tampering of the stored underlying data, and APPU is dedicated to data processing, and more particularly to facilitating barriers and synchronization for machine learning in autonomous machines, and the execution of a query and a combined teaching would have improved YAMADA in view of White performance by accessing memory in parallel.
YAMADA in view of White, and further in view of APPU further teaches the following:
said MDSC is a sequential circuit comprising a plurality of stages configured to compute at said plurality of stages in sequence (See APPU: Page 43, scheduling of all threads and/or groups of threads across a compute element without being tied down to a particular block of a compute element.).
As per claim 23, YAMADA in view of White, and further in view of APPU teaches the vector database according to claim 22, wherein a first number of said plurality of SPU's is larger than a second number of said plurality of stages (See APPU: Page 6, Within I/O subsystem 111 , system storage unit 114 can be connected to I/O hub 107 to provide a storage mechanism for computing system 100 I/O switch 116 can be used to provide an interface mechanism to enable connections between I/O hub 107 and other components, such as network adapter 118 and/or wireless networking that can be integrated into the platform Adapter 119 , and various other devices that can be added via one or more add-in devices 120 . ).
Claims 25-26 and 31 are rejected under 35 USC § 103 as being unpatentable over
YAMADA in view of White, as applied to Claims 21, 24, 27, 30 and 32 above, and further in view of
SITY et al.: "MEMORY-BASED PROCESSOR" (Korea Patent Application Publication KR 20220078566 A, DATE PUBLISHED 2022-06-10; and DATE FILED 2020-08-13, hereafter "SITY").
As per claim 25, YAMADA in view of White does not explicitly teach the vector database according to claim 21, wherein: all VDCC's of said plurality of SPU's and said MDSC are disposed on a same semiconductor substrate.
However, SITY teaches the vector database according to claim 21, wherein:
all VDCC's of said plurality of SPU's and said MDSC are disposed on a same semiconductor substrate (See Page 35, the distributed processor is disposed on a substrate (e.g., a semiconductor substrate such as silicon and/or a circuit substrate such as a flexible circuit board) on which a memory array including a plurality of discrete memory banks is disposed).
It would have been obvious to one having ordinary skill in the art at the time the Applicant's application was filed to combine SITY's teaching with YAMADA in view of White because YAMADA is dedicated to a database server, a query device, a database system, a calculation system, White is dedicated to verifying outsourced vector database query results to mitigate tampering of the stored underlying data, and SITY is dedicated to a hardware chip comprising processing elements coupled to dedicated memory banks for improving power efficiency and speed of memory chips, and a combined teaching would have improved YAMADA in view of White to improve efficiency through memory intensive operations.
YAMADA in view of White, and further in view of SITY further teaches the following:
said storage array is stacked with said VDCC and overlaps at least a portion of said VDCC within said each SPU (See SITY: Page 40: a processor on a memory chip may include a substrate and a plurality of processor subunits disposed on the substrate. The memory chip may further include a corresponding plurality of memory banks disposed on the substrate. Here the disposed reads on overlapped).
As per claim 26, YAMADA in view of White, and further in view of SITY teaches the vector database according to claim 25, wherein said plurality of SPU's and said MDSC form a mechanically-stable entity (See SITY: Page 9, Although a memory bank may include lines, any other arrangement may be utilized to place devices within a substrate to form the bank on the substrate. Also, one or more banks may be electrically coupled to at least one memory controller to form a memory array. A memory array may include a rectangular arrangement of banks, although the arrangement of banks within the array may be formed in any other shape on the substrate).
As per claim 31, YAMADA in view of White, and further in view of SITY teaches the vector database according to claim 21, further comprising
an off-array VDCC disposed outside said plurality of SPU's (See SITY: Page 5,the memory array including a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, the processing array including a plurality of processor subunits, each processor subunit of the plurality of processor subunits comprising one of the plurality of discrete memory banks),
Wherein said VDCC in said each SPU is an in-array VDCC (See SITY: Page 40, a processor on a memory chip may include a substrate and a plurality of processor subunits disposed on the substrate. The memory chip may further include a corresponding plurality of memory banks disposed on the substrate); and
said off-array VDCC implements a different vector-distance calculating algorithm than said in-array VDCC (See White: col. 8, lines 19-24, the querier (e.g., the verifier device) sends a query vector q and the vector database 112 returns the data vector or row that has the lowest distance from q. An exact nearest neighbor (ENN) search necessarily gives the closest result, while for example an approximate nearest neighbor (ANN) search gives something that is approximately, but not necessarily exactly, the closest result. Here the verifier device reads on the MDSC).
Claim 28 is rejected under 35 USC § 103 as being unpatentable over
YAMADA in view of White, as applied Claims 21, 24, 27, 30 and 32 above, and further in view of
HE et al.: "METHOD AND SYSTEM FOR INTELLIGENT IDENTIFICATION AND CORRECTION OF QUESTIONS" (United States Patent Application Publication US 20200090539 A1, DATE PUBLISHED 2020-03-19; and DATE FILED 2019-09-24, hereafter "HE").
As per claim 28, YAMADA in view of White does not explicitly teach the vector database according to claim 21, wherein: the vector database according to claim 21, wherein said VDCC is a reconfigurable VDCC configured to implement a first vector-distance calculating algorithm at a first time and a second vector-distance calculating algorithm at a second time.
However, He teaches the vector database according to claim 21, wherein:
teaches the vector database according to claim 21, wherein said VDCC is a reconfigurable VDCC configured to implement a first vector-distance calculating algorithm at a first time and a second vector-distance calculating algorithm at a second time (See [0203], the "Distance" between vectors is commonly used as the Similarity Measurement between different vectors, the commonly used distance comprises: Euclidean distance, Manhattan distance, and angle cosine (Cosine) and so on. The calculation method adopted in this embodiment is the angle cosine.).
It would have been obvious to one having ordinary skill in the art at the time the Applicant's application was filed to combine He's teaching with YAMADA in view of White because YAMADA is dedicated to a database server, a query device, a database system, a calculation system, White is dedicated to verifying outsourced vector database query results to mitigate tampering of the stored underlying data, and HE is dedicated to auto-correcting an answer sheet containing multiple types of questions, the combined teaching of YAMADA, White and HE references would have enabled YAMADA in view of White to improve on-chip vector database search by using intelligent identification of a search.
Claims 29 … are rejected under 35 USC § 103 as being unpatentable over
YAMADA in view of White, , as applied Claims 21, 24, 27, 30 and 32 above, and further in view of
Tsutom et al.: "VIDEO ENCODING APPARATUS" (Canada Patent CA-1282166, DATE PUBLISHED 1991-03-26; and DATE FILED 1986-01-15, hereafter "Tsutom").
As per claim 29, YAMADA in view of White does not explicitly teach the vector database according to claim 21, wherein said MDSC is a binary-tree comparison circuit.
However, Tsutom teaches the vector database according to claim 21, wherein said MDSC is a binary-tree comparison circuit (See Page 8, lines 2-3 and Page 84, lines 3-6, a vector quantization apparatus wherein a binary tree k-dimensional vector space, and the distortion comparison circuit 445 selects one output vector to give the minimum distortion and then outputs 5 the distortion comparison result signal V9 based on the comparison results).
It would have been obvious to one having ordinary skill in the art at the time the Applicant's application was filed to combine Tsutom's teaching with YAMADA in view of White because YAMADA is dedicated to a database server, a query device, a database system, a calculation system, White is dedicated to verifying outsourced vector database query results to mitigate tampering of the stored underlying data, and Tsutom is dedicated to providing a video encoding apparatus, the combined teaching of YAMADA, White and Tsutom references would have enabled YAMADA in view of White to select the minimum distance from a spectrum of calculated vector distances when irregularity of calculation can be suppressed and made minimum.
Related Prior Arts
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure can be found in the PTO-892 Notice of Reference Cited.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. SEE MPEP 2141.02 [R-5] VI. PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS: A prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984) In re Fulton, 391 F.3d 1195, 1201, 73 USPQ2d 1141, 1146 (Fed. Cir. 2004). >See also MPEP §2123.
In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KUEN S LU whose telephone number is (571)272-4114. The examiner can normally be reached on M-F, 8-19, Mid-Flex 2 hours.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Aleksandr Kerzhner can be reached on 571-270-1760. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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KUEN S LU /Kuen S Lu/
Art Unit 2156
Primary Patent Examiner
February 26, 2026