DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to because In Fig. 12 items 141 and 142 are not labeled. In Figs. 14, 15, and 16 . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,2,6,9, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Isono (US 11439006 hereinafter Isono).
In regards to claim 1, Isono discloses;” A flexible printed circuit (abstract), comprising a bending (Fig. 1 (shown as narrow region) portion and a soldering portion (Fig. 1 area where contact are located) connected to the bending portion, wherein the flexible printed circuit comprises a plurality of conductive layers (Fig. 9 (33,34, and 39)), a plurality of insulation layers (Fig. 9 (21, 22, and 23)), and a first protective layer (Fig. 9 (5)), and each of the plurality of insulation layers is disposed between two adjacent conductive layers of the plurality of conductive layers (Fig. 9); the plurality of conductive layers comprise a soldering layer and a trace layer (Fig. 9 (shown)), the soldering layer is located in the soldering portion, the soldering layer is one surface layer of the soldering portion, the soldering layer is formed by a plurality of pads that are spaced from each other (Fig. 9 (31A, 32)), the trace layer is located on a side of the soldering layer and extends from the soldering portion to the bending portion (Fig. 9 (shown)), and the pad is connected to the trace layer by using a through hole conductor (Fig. 9 (36A) Col. 12, Lines 65-67)); and the first protective layer is located on a side that is of the trace layer and that is away from the soldering layer, the first protective layer extends from the soldering portion to the bending portion (Fig. 9 (shown)), a part of the first protective layer located in the soldering portion forms the other surface layer of the soldering portion, and a part of the first protective layer located in the bending portion forms one surface layer of the bending portion(Fig. 9 (shown)).”
In regards to claim 2, Isono discloses;” The flexible printed circuit according to claim 1, wherein the trace layer comprises a conductor block and a trace, the conductor block is located in the soldering portion, one end of the trace is connected to the conductor block (Fig. 3C (31A)), the other end of the trace extends to the bending portion, and the pad is connected to the conductor block by using the through hole conductor (Fig. 9 (shown),Col.12, Lines 65-67).”
In regards to claim 6, Isono discloses;” The flexible printed circuit according to claim 1, wherein the plurality of insulation layers comprise a first insulation layer, wherein the first insulation layer is located between the soldering layer and the adjacent trace layer, and extends from the soldering portion to the bending portion, and a part of the first insulation layer located in the bending portion forms the other surface layer of the bending portion (Fig. 9 (shown)).”
In regards to claim 9, Isono discloses;” A circuit board assembly, comprising a circuit board and a flexible printed circuit (abstract, Fig. 7 (11, 12)), wherein the flexible printed circuit comprising a bending portion (Fig. 1 (shown as narrow region) and a soldering portion connected to the bending portion (Fig. 1 area where contacts are located), wherein the flexible printed circuit comprises a plurality of conductive layers (Fig. 9 (33,34, and 39)), a plurality of insulation layers (Fig. 9 (21, 22, and 23)), and a first protective layer (Fig. 9 (5)), and each of the plurality of insulation layers is disposed between two adjacent conductive layers of the plurality of conductive layers (Fig. 9); the plurality of conductive layers comprise a soldering layer and a trace layer(Fig. 9 (shown)), the soldering layer is located in the soldering portion, the soldering layer is one surface layer of the soldering portion, the soldering layer is formed by a plurality of pads that are spaced from each other (Fig. 9 (31A, 32)), the trace layer is located on a side of the soldering layer and extends from the soldering portion to the bending portion (Fig. 9 (shown)), and the pad is connected to the trace layer by using a through hole conductor (Fig. 9 (36A) Col. 12, Lines 65-67)); and the first protective layer is located on a side that is of the trace layer and that is away from the soldering layer, the first protective layer extends from the soldering portion to the bending portion (Fig. 9 (shown)), a part of the first protective layer located in the soldering portion forms the other surface layer of the soldering portion, and a part of the first protective layer located in the bending portion forms one surface layer of the bending portion; wherein a soldering portion of the flexible printed circuit is soldered to the circuit board (Fig. 9 (shown)).”
In regards to claim 10, Isono discloses;” The circuit board assembly according to claim 9, wherein the trace layer comprises a conductor block (Fig. 3C (31A)) and a trace, the conductor block is located in the soldering portion, one end of the trace is connected to the conductor block, the other end of the trace extends to the bending portion, and the pad is connected to the conductor block by using the through hole conductor (Fig. 9 (36A) Col. 12, Lines 65-67)).”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Isono (US 11439006 hereinafter Isono), and in view of DeRosa et al. (US 20160381804 hereinafter DeRosa).
In regards to claim 17, Isono discloses;” An electronic device (Col. 1, Lines 19-21), and a circuit board assembly, wherein the circuit board assembly, comprising a circuit board (Fig. 7, (11, 12)) and a flexible printed circuit (Fig. 9), wherein the flexible printed circuit comprising a bending portion(Fig. 1 (shown as narrow region) and a soldering portion connected to the bending portion (Fig. 1 area where contacts are located), wherein the flexible printed circuit comprises a plurality of conductive layers (Fig. 9 (33,34, and 39)), a plurality of insulation layers (Fig. 9 (21, 22, and 23)), and a first protective layer (Fig. 9 (5)), and each of the plurality of insulation layers is disposed between two adjacent conductive layers of the plurality of conductive layers (Fig. 9); the plurality of conductive layers comprise a soldering layer and a trace layer (Fig. 9 (shown)), the soldering layer is located in the soldering portion, the soldering layer is one surface layer of the soldering portion, the soldering layer is formed by a plurality of pads (Fig. 9 (31A, 32)) that are spaced from each other, the trace layer is located on a side of the soldering layer and extends from the soldering portion to the bending portion (Fig. 9 (shown)), and the pad is connected to the trace layer by using a through hole conductor (Fig. 9 (36A) Col. 12, Lines 65-67)); and the first protective layer is located on a side that is of the trace layer and that is away from the soldering layer, the first protective layer extends from the soldering portion to the bending portion, a part of the first protective layer located in the soldering portion forms the other surface layer of the soldering portion, and a part of the first protective layer located in the bending portion forms one surface layer of the bending portion; wherein a soldering portion of the flexible printed circuit is soldered to the circuit board (Fig. 9 (shown))”, but does not directly disclose “a housing and wherein the circuit board assembly is installed inside the housing.”
However, DeRosa discloses a flexible interconnect structure used within a housing as disclosed in paragraph 0029 and shown in Fig. 4 (402). It would have been obvious to a skilled artisan to use a flexible wiring structure within a supporting housing structure. Flexible wiring is used in many applications such as cell phone, cameras and the like, where high density interconnections are required. Therefore, using a housing as disclosed by DeRosa with the wiring structure of Isono, the claimed invention is disclosed.
Claim(s) 4, 12, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Isono (US 11439006 hereinafter Isono) as applied to claims 2, 10, and 18, in view of J.B. COOK (US 3221095 hereinafter cook) and further in view of DeRosa et al. (US 20160381804 hereinafter DeRosa).
In regards to claim 4, Isono discloses;” The flexible printed circuit according to claim 2”, but does not directly disclose;” a quantity of the trace layer is more than one, and a plurality of conductor blocks connected to the plurality of pads are located on different trace layers.”
However, Cook discloses a flexible printed circuit structure that has terminals located at an end, and comprises of multiple signal layers connecting to thru holes as shown in figure 2, 3 and 4. It would have been obvious to a skilled artisan to include multiple signal layers when forming a high density flexible circuit board that interconnect different devices. In modern packaging there is a need to interconnect multiple devices with a large number of signal, thus a higher density wiring structure is needed. Therefore, using the structure as disclosed by Cook with the structure of Isono, the claimed invention is disclosed.
In regards to claim 12, Isono discloses;” The circuit board assembly according to claim 10”, but does not directly disclose;” a quantity of the trace layer is more than one, and a plurality of conductor blocks connected to the plurality of pads are located on different trace layers.”
However, Cook discloses a flexible printed circuit structure that has terminals located at an end, and comprises of multiple signal layers connecting to thru holes as shown in figure 2, 3 and 4. It would have been obvious to a skilled artisan to include multiple signal layers when forming a high density flexible circuit board that interconnect different devices. In modern packaging there is a need to interconnect multiple devices with a large number of signal, thus a higher density wiring structure is needed. Therefore, using the structure as disclosed by Cook with the structure of Isono, the claimed invention is disclosed.
In regards to claim 20, a modified Isono discloses;” The electronic device according to claim 18”, but does not directly disclose;” a quantity of the trace layer is more than one, and a plurality of conductor blocks connected to the plurality of pads are located on different trace layers.”
However, Cook discloses a flexible printed circuit structure that has terminals located at an end, and comprises of multiple signal layers connecting to thru holes as shown in figure 2, 3 and 4. It would have been obvious to a skilled artisan to include multiple signal layers when forming a high density flexible circuit board that interconnect different devices. In modern packaging there is a need to interconnect multiple devices with a large number of signal, thus a higher density wiring structure is needed. Therefore, using the structure as disclosed by Cook with the structure of a modified Isono, the claimed invention is disclosed.
Allowable Subject Matter
Claim3, 5, 7, 8, 11, 13-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL F MCALLISTER whose telephone number is (571)272-2453. The examiner can normally be reached Monday-Friday 7 AM-4 PM.
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/MICHAEL F MCALLISTER/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
