Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 12/25/2024. Claims 1 -12 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-2, 4-7, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tao Lui WO 2020238227 Public more than 1 year of the effective filing date of the application.
Fig. 1 and Fig. 2 of Tao Lui discloses a pipelined analog-to-digital converter, comprising a plurality of pipeline stages cascaded in sequence, wherein at least one of the pipeline stages (Fig. 2) comprises: a N-bit sub-analog-to-digital conversion module (Sub ADC) configured to receive an analog input signal (Vinp Vinn) and perform analog-to-digital conversion (SubADC) on the analog input signal (Vinp, Vinn) to obtain and output 2N digital signals (output of SubADC); a first sub-digital-to-analog conversion module (SubDAC 1) configured to receive 2N-1 digital signals and perform digital-to-analog conversion (SubDAC 1) on the 2N-1 digital signals (output SubADC) to obtain and output a first analog signal (fist analog signal Vc); a second sub-digital-to-analog conversion module (SubDAC 2) configured to receive other 2N-1 digital signals (output of SubADC) and perform digital-to-analog conversion (subDAC 2) on the other 2N-1 digital signals (other output of SubADC) to obtain and output a second analog signal (second analog signal Vc); and a switched capacitor amplification module (switching capaciator of OTA) configured to receive the first analog signal (first analog signal Vc) and the second analog signal (second analog signal Vc), perform a difference operation (differential operation of OTA) on the first analog signal (first analog signal Vc) and the second analog signal (second analog signal Vc), and perform an amplification operation (amplification operation of OTA) on a result of the difference operation (differential operation of OTA), to obtain and output an analog output signal (Voutp, Voutn), and wherein N is an integer greater than or equal to 1 (2n-1 output of SubADC wherein n = or >1.)
Regarding claim 2. The pipelined analog-to-digital converter according to claim 1, Figs 2, 3, and 5 of Tao Lui further discloses wherein the N-bit sub-analog-to-digital conversion module (SubADC) comprises: a first resistor divider unit (RA(2) in Fig. 3) configured to perform voltage division processing (V<2n-1>… V<1>) on an initial reference voltage VRP, VRN) and output 2N non-inverting reference voltages (Vrefp) to outside; a second resistor divider unit (RA(1) in Fig. 3) configured to perform voltage division processing ((V<2n-1>… V<1>) on the initial reference voltage (VRP, VRN) and output 2N inverting reference voltages (Vrefn) to the outside; and a comparator array unit (Fig. 5) connected to the first resistor divider unit (RA(2)) and the second resistor divider unit (RA(1)) respectively, the comparator array unit (COPM (2n-1)…COMP (1) in Fig. 5) configured to receive the analog input signal (Vinp, Vinn) and compare unit (CPM (2n-1)…COMP (1) in Fig. 5) the analog input signal (Vinp, Vinn) with 2N reference voltages (Vref <2n-1….Vref <1>) respectively, to obtain the 2N digital signals (DP1<2n-1>…DP1<1> or DN1<2n-1>…DN1<1>) , wherein the 2N digital signals (DP1<2n-1>…DP1<1> or DN1<2n-1>…DN1<1>) comprise 2N-1 first digital signals (DP1<2n-1) and 2N-1 second digital signals (DN1<2n-1>…DN1<1>), and the 2N non-inverting reference voltages (Vrefp <2n-1>…Vrefp <1>) correspond one-to-one to the 2N inverting reference voltages (Vrefn <2n-1>…Vrefn <1>) to constitute the 2N reference voltages (2n of reference voltages of RA(2) and RA(1))
Regarding claim 4. The pipelined analog-to-digital converter according to claim 2, Figs. 3 and 4 further discloses wherein the first resistor divider unit (RA(2)) comprises a first input port (VRP), a second input port (VRN), and 2N+1 first resistors (Fig. 4), and the 2N+1 first resistors (Fig. 4) are connected in series between the first input port (VRP) and the second input port (VRN) in sequence, the first input port (VRP) is connected to a positive end (VRP end) of the initial reference voltage (VRP), the second input port (VRN) is connected to a negative end (VRN end) of the initial reference voltage (VRN), and each common end (common end of resistors) of each two adjacent first resistors (two adjacent resistors) outputs the non-inverting reference voltage (Vrefp of V2n-1…V<1>).
Regarding claim 5. The pipelined analog-to-digital converter according to claim 2, Fig. 3 and Fig. 4 further discloses wherein the second resistor divider unit (RA(1)) comprises a third input port (VRP input port of (RA (1)), a fourth input port, and 2N+1 second resistors (Fig. 4) , and the 2N+1 second resistors (Fig. 4) are connected in series between the third input port (VRP port of RA(1) and the fourth input port in sequence (VRN input port of RA(1)), the third input port (VRP input port of RA(1) is connected to a negative end of the initial reference voltage (VRN reference voltage) , the fourth input port (VRN input port of (RA(1)) is connected to a positive end of the initial reference voltage (VRP voltage) , and each common end of each two adjacent second resistors (common end of two series resistor) outputs the inverting reference voltage (Vrefn of V2n-1…V<1>).
Regarding claim 6. The pipelined analog-to-digital converter according to claim 5, Figs: 2-5 further discloses wherein the comparator array unit (Fig. 5) comprises: 2N comparators (COMP(2n-1…COMP(1)) configured to compare and quantize the analog input signal (Vip, Vin) with the 2N reference voltages (Vrefp <2n-1>…Vrefp <1>) one by one and output 2N-1 first initial digital signals (DP1<1>…DP1<2n-1>) and 2N-1 second initial digital signals (DN1<2n-1>… DN1<1>); and 2n drivers (BUF (1)….BUF (2n-1)) , wherein input ends of the 2N drivers (BUF (1)….BUF (2n-1)) are connected to output ends of the 2N comparators (COMP(2n-1…COMP(1)) in a one-to-one correspondence, and output ends of the 2N drivers ((BUF (1)….BUF (2n-1)) output the 2N-1 first digital signals (DP1<1>…DP1<2n-1>) and the 2N-1 second digital signals (DN1<2n-1>… DN1<1>) controlled by a first clock signal (CK).
Regarding claim 7. The pipelined analog-to-digital converter according to claim 6, Figs: 2-5 further discloses wherein the 2N comparators (COMP(2n-1…COMP(1)) are arranged in parallel; in an i-th comparator (COMP(1) , a first input end (Vin+) of the i-th comparator (COMP(1))is connected to a positive end of the analog input signal (Vip) , a second input end (Vin-) of the i-th comparator (COMP(1)) is connected to a negative end of the analog input signal (Vin) , a third input end (Vref+) of the i-th comparator (COMP(1)) is connected to an i-th non-inverting reference voltage (Vrefp<1>), and a fourth input end (Vref-) of the i-th comparator (COMP(1)) is connected to an i-th inverting reference voltage (Vrefn <1>), wherein i = 1, 2,..., 2N; the 2N drivers (((BUF (1)….BUF (2n-1)) are arranged in parallel; in an i-th said driver (((BUF (1)….BUF (2n-1)), a first input end (A1) of the i-th driver (BUB(1)) is connected to a first output end (OP) of the i-th comparator (COMP(1)), a second input end (A2) of the i-th driver (BUF(1)) is connected to a second output end (ON) of the i-th comparator (COMP(1)), and a third input end (A4) of the i-th driver (BUF(1)) is connected to the first clock signal (CK); and an output end (OP) of an m-th comparator (COMP(3)) outputs the first initial digital signal (A1), an output end of an m-th driver (BUF(3)) outputs the first digital signa (DP1<3>), an output end (OP) of an n-th comparator (COMP(2n-1)) outputs the second initial digital signal (A1) , and an output end of an n-th driver (BUF (2n-1)) outputs the second digital signal (DP!<2n-1>, wherein m is an odd number (1, 3, 5) from 1 to 2N, and n is an even number (2, 4, 6) from 1 to 2N.
Regarding claim 9. The pipelined analog-to-digital converter according to claim 7, Fig. 2, Fig. 8 and Fig. 9 further disclose wherein the first sub-digital-to-analog conversion module (SubDAC (1)) comprises 2N-1 first switched capacitor units arranged in parallel (2N-1 switching capacitor units arranged in parallel of each subDAC1), a first input end (G1 in Fig. 9) of a j-th first switched capacitor unit (M22, M23, M24 in Fig. 9) is connected to a second clock signal (Ø in Fig. 8), a second input end (V1 in Fig. 9) of the j-th first switched capacitor unit (M22, M23, M24 in Fig. 9) is connected to the positive end of the analog input signal (Vin in Fig. 8), a third input end (V3 in Fig. 9) of the j-th first switched capacitor unit(M22, M23, M24) is connected to the positive end of the initial reference voltage (VRP in Fig. 8), a fourth input end (V2 in Fig. 9) of the j-th first switched capacitor unit (M22, M23, M24 in Fig. 9) is connected to the negative end of the initial reference voltage (VRN in Fig. 8) , a fifth input end (G3 in Fig. 8) of the j-th first switched capacitor unit (M22, M23, M24) is connected to a negative end of a j-th first digital signal (CK2<2> in Fig. 8), a sixth input end (G2) of the j-th first switched capacitor unit (M22, M23, M24) is connected to a positive end of the j-th first digital signal (CK1), and output ends of the 2N-1 first switched capacitor units (output end of subDAC in Fig. 9) are connected in parallel and output the first analog signal (analog output D in Fig. 9) to the outside, wherein j= 1, 2,..., 2N-1; and the second sub-digital-to-analog conversion (SubDAC (2)) in Fig. 8) module comprises 2N-1 second switched capacitor units arranged in parallel (2N-1 switching capacitor units arranged in parallel of each subDAC (2)), a first input end of a j-th second switched capacitor unit is connected to the second clock signal, a second input end of the j-th second switched capacitor unit is connected to the negative end of the analog input signal, a third input end of the j-th second switched capacitor unit is connected to the positive end of the initial reference voltage, a fourth input end of the j-th second switched capacitor unit is connected to the negative end of the initial reference voltage, a fifth input end of the j-th second switched capacitor unit is connected to a positive end of a j-th second digital signal, a sixth input end of the j-th second switched capacitor unit is connected to a negative end of the j-th second digital signal, and output ends of the 2N-1 second switched capacitor units are connected in parallel and output the second analog signal to the outside (similar rational Fig. 8 and Fig. 9 as applied to the first subDAC (1) in the claim).
Regarding claim 10. The pipelined analog-to-digital converter according to claim 9, Fig. 9 further discloses wherein the first switched capacitor unit (M22, M23, M24 for subDAC (1)) comprises a first NMOS transistor (M22) , a second NMOS transistor (M23) , a first PMOS transistor (M24), and a switched capacitor (CU), and a gate of the first NMOS transistor (gate of M22) serves as a first input end (G1) of the first switched capacitor unit (M22, M23, M24 for subDAC (1), a drain of the first NMOS transistor (drain of M22) serves as a second input end (V1) of the first switched capacitor unit (M22, M23, M24), a gate of the second NMOS transistor (gates of M23) serves as a sixth input end (G2) of the first switched capacitor unit (M22, M23, M24 for subDAC (1)), a drain of the second NMOS transistor (drain of M23) serves as a fourth input end (V2) of the first switched capacitor unit (M22, M23, M24 for subDAC (1)), a gate of the first PMOS transistor (gate of M24) serves as a fifth input end (G3) of the first switched capacitor unit (M22, M23, M24), a source of the first PMOS transistor (source of M24) serves as a third input end (V3) of the first switched capacitor unit (M22, M23, M24 for subDAC (1), a source of the first NMOS transistor (source of M22) , a source of the second NMOS transistor (source or M23) , and a drain of the first PMOS transistor (drain of M24) are respectively connected to a first end of the switched capacitor (first end of CU), and a second end of the switched capacitor (second end of CU) serves as an output end (D) of the first switched capacitor unit (M22, M23, M24 for subDAC (1)).
Allowable Subject Matter
5. Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: : a drain of the third NMOS transistor and a drain of the fifth NMOS transistor are respectively connected to a basic signal, a source of the fifth NMOS transistor, a drain of the fourth NMOS transistor, a non-inverting input end of the fully differential operational amplifier, an output end of the first sub-digital-to-analog conversion module, and a first end of the first capacitor are connected together, a second end of the first capacitor, an inverting output end of the fully differential operational amplifier, and a drain of the sixth NMOS transistor are connected together, a source of the third NMOS transistor, a source of the fourth NMOS transistor, an inverting input end of the fully differential operational amplifier, an output end of the second sub-digital-to-analog conversion module, and a first end of the second capacitor are connected together, a second end of the second capacitor, a non-inverting output end of the fully differential operational amplifier, and a source of the sixth NMOS transistor are connected together, and a gate of the sixth NMOS transistor is connected to a fourth clock signal, the non-inverting output end of the fully differential operational amplifier serves as a positive output end of the switched capacitor amplification module, and the inverting output end of the fully differential operational amplifier serves as a negative output end of the switched capacitor amplification module.
6. Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the driver comprises a first NAND gate, a first NOR gate, a first NOT gate, a second NOT gate, and a third NOT gate, and a first input end of the first NAND gate serves as a first input end of the driver, a second input end of the first NAND gate is connected to an output end of the first NOT gate, an output end of the first NAND gate is connected to an input end of the second NOT gate, an output end of the second NOT gate serves as a second output end of the driver, an input end of the first NOT gate serves as a third input end of the driver, a first input end of the first NOR gate is connected to the input end of the first NOT gate, a second input end of the first NOR gate serves as a second input end of the driver, an output end of the first NOR gate is connected to an input end of the third NOT gate, and an output end of the third NOT gate serves as a first output end of the driver.
7. Claims 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: a drain of the third NMOS transistor and a drain of the fifth NMOS transistor are respectively connected to a basic signal, a source of the fifth NMOS transistor, a drain of the fourth NMOS transistor, a non-inverting input end of the fully differential operational amplifier, an output end of the first sub-digital-to-analog conversion module, and a first end of the first capacitor are connected together, a second end of the first capacitor, an inverting output end of the fully differential operational amplifier, and a drain of the sixth NMOS transistor are connected together, a source of the third NMOS transistor, a source of the fourth NMOS transistor, an inverting input end of the fully differential operational amplifier, an output end of the second sub-digital-to-analog conversion module, and a first end of the second capacitor are connected together, a second end of the second capacitor, a non-inverting output end of the fully differential operational amplifier, and a source of the sixth NMOS transistor are connected together, and a gate of the sixth NMOS transistor is connected to a fourth clock signal, the non-inverting output end of the fully differential operational amplifier serves as a positive output end of the switched capacitor amplification module, and the inverting output end of the fully differential operational amplifier serves as a negative output end of the switched capacitor amplification module.
Contact Information
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 9:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
06/05/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
Prosecution Insights