Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the application filed on 12/25/2024.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawing
The drawings filed on 12/25/2024 are objected. New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application, because figure 5 is a duplicate of figure 4. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/25/2024 is in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has been considered by the examiner.
Claims 1-13 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability should not be negated by the manner in which the invention was made.
Claims 1-4, 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (AAPA) in view of Sun (US 2016/0288601 A1).
In re to claim 1, AAPA discloses a current comparison circuit (i.e. 11, fig. 1) for a power converter (i.e. 10, see par. [0071]), comprising: a current reconstruction module (i.e. 111), used to generate a current reconstruction signal with a predetermined slope (i.e. see par. [0071]); a selector (i.e. 14), used to select one of an inductor current detection signal (i.e. Isen) the power converter (i.e. 10) or the current reconstruction signal (i.e. Isim) as a detection signal according to the selection signal (i.e. Isen1, see Pars. [0006, 0014]); and a first comparator (i.e. CMPO, see fig. 1), used to compare the detection signal with a first reference voltage (i.e. Vref1) to generate a comparison signal (i.e. Vc), wherein, the comparison signal is used to adjust duty cycle of a switching control signal (i.e. VQ) of the power converter (i.e. 10, fig. 1, see par. [0071]). Except, AAPA fails to explicitly disclose that a judgment module, used to generate a selection signal according to a DC input voltage and a DC output voltage of the power converter. Whereas, Sun teaches that a judgment module (i.e. 701/702, fig. 7) used to generate a selection signal (i.e. V1) according to a DC input voltage (i.e. VIN) and a DC output voltage (i.e. VOUT) of the power converter (i.e. fig. 7, see pars. [0027-0029]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power converter of AAPA by incorporating the judgment module of Sue to adjust the switching control signal of the power converter.
In re to claim 2, AAPA discloses the current comparison circuit (i.e. 11, fig. 1) of claim 1. Except, AAPA fails to explicitly disclose that wherein the judgment module determines whether the on time of the switching control signal is less than a predetermined time value according to the DC input voltage and the DC output voltage, when the on time is less than the predetermined time value, the selection signal is used to select the current reconstruction signal as the detection signal, when the on time is greater than or equal to the predetermined time value, the selection signal is used to select the inductor current detection signal as the detection signal. Whereas Sun teaches that the judgment module (i.e. 701/702, fig. 7) determines whether the on time of the switching control signal (i.e. V1) is less than a predetermined time value according to the DC input voltage (i.e. VIN) and a DC output voltage (i.e. VOUT), when the on time is less than the predetermined time value, the selection signal is used to select the current reconstruction signal as the detection signal (i.e. see par. [0020]), when the on time is greater than or equal to the predetermined time value, the selection signal is used to select the inductor current detection signal as the detection signal (i.e. see par. [0020-0021]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power converter of AAPA by incorporating the judgment module of Sue to adjust the switching control signal of the power converter.
In re to claim 3, AAPA discloses the current comparison circuit (i.e. 11, fig. 1) of claim 2. Except, AAPA fails to explicitly disclose that wherein the switching control signal has a fixed switching cycle, the judgment module obtains a conversion ratio of the power converter according to the DC input voltage and a DC output voltage and determines whether the on time of the switching control signal is less than a predetermined time value according to the conversion ratio. Whereas Sun teaches that the judgment module (i.e. 701, fig. 7) obtains a conversion ratio of the power converter according to the DC input voltage (i.e. VIN) and a DC output voltage (i.e. VOUT) and determines whether the on time of the switching control signal is less than a predetermined time value according to the conversion ratio (i.e. fig. 7, see pars. [0027-0029]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power converter of AAPA by incorporating the judgment module of Sue to adjust the switching control signal of the power converter. Except, Sun fails to explicitly disclose that wherein the switching control signal has a fixed switching cycle. However, Sue discloses the claimed invention except for not explicitly stating “fixed switching cycle”. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a fixed switching cycle in power converter switching circuit, since it was known in the art that switching frequency or cycle are implemented as needed or desired for the power converter.
In re to claim 4, AAPA discloses the current comparison circuit (i.e. 11, fig. 1) of claim 2. Except, AAPA fails to explicitly disclose that wherein the switching control signal has a varied switching cycle, the judgment module obtains a conversion ratio of the power converter according to the DC input voltage and a DC output voltage and determines whether the on time of the switching control signal is less than a predetermined time value according to the conversion ratio and the switching cycle. Whereas Sun teaches that the judgment module (i.e. 701, fig. 7) obtains a conversion ratio of the power converter according to the DC input voltage (i.e. VIN) and a DC output voltage (i.e. VOUT) and determines whether the on time of the switching control signal is less than a predetermined time value according to the conversion ratio and the switching cycle (i.e. fig. 7, see pars. [0027-0029]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power converter of AAPA by incorporating the judgment module of Sue to adjust the switching control signal of the power converter. Except, Sue fails to explicitly disclose that wherein the switching control signal has a fixed switching cycle. However, Sue discloses the claimed invention except for not explicitly stating “fixed switching cycle”. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a fixed switching cycle in power converter switching circuit, since it was known in the art that switching frequency or cycle are implemented as needed or desired for the power converter.
In re to claim 6, AAPA discloses the current comparison circuit (i.e. 11, fig. 1) of claim 2. Except, AAPA fails to explicitly disclose that wherein the judgment module comprises: a comparison module, used to determine whether the conversion ratio of the power converter is less than a predetermined value according to the relationship between the DC input voltage and the DC output voltage. Whereas Sue teaches that the judgment module (i.e. 701/702, fig. 7) comprises: a comparison module (i.e. 701, fig. 3) used to determine whether the conversion ratio of the power converter (i.e. fig. 7) is less than a predetermined value according to the relationship between the DC input voltage (i.e. VIN) and the DC output voltage (i.e. VOUT, see pars. [0027-0029]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power converter of AAPA by incorporating the judgment module of Sue to adjust the switching control signal of the power converter.
In re to claim 13, AAPA discloses a power converter (i.e. fig. 1), wherein comprising: a power stage circuit (i.e. Q1, Q2, L and Co); the current comparison circuit (i.e. 11) of to claim 1, used to obtain a comparison signal of inductor current (i.e. IL) and the comparison signal is used to adjust the duty cycle of the switching control signal (i.e. Vo) of the power converter (i.e. fig. 1); a logic and driving circuit (i.e. 12), to receive the comparison signal (i.e. Vc) output by the current comparison circuit (i.e. 11), to output a switching control signal (i.e. Vo) according to the comparison signal (i.e. Vc) to control the on/off states of a main switch transistor (i.e. Q1) in the power stage circuit (i.e. Q1, Q2, L and Co, see fig. 1 and pars. [0070-0071]).
Allowable Subject Matter
Claims 5, and 7-12 are objected to as being dependent upon a rejected base claims but
would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In re to claim 5, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein when the on time is less than the predetermined time value, the selection signal is further used to enable the minimum off time limit of the switching control signal, when the on time is greater than or equal to the predetermined time value, the selection signal is also used to enable the minimum on time limit of the switching control signal”.
In re to claim 7, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the comparison module comprises: a first resistor network, used to obtain a proportional signal of the DC input voltage according to a predetermined proportional coefficient, and the proportional coefficient is equal to a predetermined value of the conversion ratio”
In re to claim 8, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “a divider, used to divide the DC output voltage by the DC input voltage to obtain a voltage signal representing the proportional coefficient; and a third comparator, used to compare the voltage signal representing the proportional coefficient with a third reference voltage to generate the selection signal”.
In re to claim 9, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “a divider, used to divide the DC output voltage by the DC input voltage to obtain a voltage signal representing the proportional coefficient; a time-to-voltage module, used to convert the switching cycle of the switching control signal into a voltage signal representing the switching cycle; a multiplier, used to multiply the voltage signal representing the proportional coefficient with the voltage signal representing the switching cycle to obtain a voltage signal representing the on time; and a fourth comparator, used to compare the voltage signal representing the on time with a fourth reference voltage to generate the selection signal”.
In re to claim 10, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “switch discharges the capacitor periodically under the control of a clock signal, to generate a proportional signal of the DC input voltage on the capacitor; a fifth comparator, used to compare the DC output voltage with the proportional signal of the DC input voltage generated on the capacitor to generate the selection signal; and a latch, used to latch the selection signal under the control of the clock signal”.
In re to claim 11, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “a transistor and a first resistor, connected in series at the first current path of the current mirror; and an operational amplifier, wherein the positive input terminal of the operational amplifier receives the proportional signal of the DC input voltage obtained by the second resistor network, and the negative input terminal is connected to the intermediate node between the transistor and the first resistor, and the output terminal is connected to the control terminal of the transistor, wherein, the second current path of the current mirror provides the output current of the voltage controlled current source”.
The art of record does not disclose the above limitations, nor would it be obvious to modify the art of record to include either of the above limitations.
In re to claim 12, claim 12 depends on claim 11, thus it is also objected for the same reasons provided above.
Remarks
The examiner has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
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/YEMANE MEHARI/Primary Examiner, Art Unit 2838
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