DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species V in the reply filed on January 22, 2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. PG Pub 2022/0180801) in view of Sudo (U.S. PG Pub 2002/0105373).
Regarding Claim 16, Kim et al. teaches an electronic device, comprising:
a first transistor (Figure 8, Element NT2. Paragraph 48), comprising a first end (Figure 8, Element ground. Paragraph 48) and a first control end (Figure 8, Element NA. Paragraph 48);
a second transistor (Figure 8, Element NT1. Paragraph 48), comprising a second control end (Figure 8, Element IP2. Paragraph 46), the second control end (Figure 8, Element IP2. Paragraph 46) for receiving a pulse signal (Figure 8, Element SS. Paragraphs 46 - 48) having a pulse width (Figure 9, Element TON. Paragraph 70) and a pulse amplitude (Figure 9, Element not labeled, but is the amplitude of signal SS. Paragraph 70);
a driver transistor (Figure 8, Element NT4. Paragraph 48), comprising a third control end (Figure 8, Element GN. Paragraph 50), the third control end (Figure 8, Element GN. Paragraph 50) being coupled to the first control end (Figure 8, Element NA. Paragraph 48); and
a first electronic unit (Figure 8, Element GN. Paragraph 53), coupled to the driver transistor (Figure 8, Element NT4. Paragraph 48);
wherein a magnitude of a current flowing through the first electronic unit (Figure 8, Element GN. Paragraph 53) is modulated according to the pulse amplitude (Figure 9, Element not labeled, but is the amplitude of signal SS. Paragraph 70), and a duration of the current flowing through the first electronic unit (Figure 8, Element GN. Paragraph 53) is modulated according to the pulse width (Figure 9, Element TON. Paragraph 70).
Kim et al. is silent with regards to the second control end being coupled to the first end.
Sudo teaches the second control end (Figure 14, Element not labeled, but is the gate of Element 62. Paragraph 62) being coupled to the first end (Figure 14, Element VDDU. Paragraph 61).
It would have been obvious to a person of ordinary skill of the art to modify the display device of Kim et al. with the driver circuit of Sudo. The motivation to modify the teachings of Kim et al. with the Sudo is to reduce power consumption, as taught by Sudo (Paragraph 11).
Regarding Claim 17, Kim et al. in view of Sudo teach the electronic device of claim 16 (See Above). Kim et al. teach further comprising: a third transistor (Figure 8, Element OFFT. Paragraph 69), comprising:
a first end (Figure 8, Element ground. Paragraph 48), coupled to a first system voltage end (Figure 8, Element ground. Paragraph 48);
a second end (Figure 8, Element GN. Paragraph 53), coupled to the first control end (Figure 8, Element NA. Paragraph 48); and
a current source (Figure 8, Element ground. Paragraph 57), coupled to a second end (Figure 8, Element IP1. Paragraph 48) of the second transistor (Figure 8, Element NT1. Paragraph 48).
Kim et al. is silent with regards to a third transistor (Figure 14, Element 61. Paragraph 62) comprising a control end (Figure 14, Element 61, Sub-Element not labeled, but is the gate. Paragraph 62), coupled to the first end (Figure 14, Element VDDU. Paragraph 61) of the first transistor (Figure 14, Element 16. Paragraph 62).
It would have been obvious to a person of ordinary skill of the art to modify the display device of Kim et al. with the driver circuit of Sudo. The motivation to modify the teachings of Kim et al. with the Sudo is to reduce power consumption, as taught by Sudo (Paragraph 11).
Regarding Claim 18, Kim et al. in view of Sudo teach the electronic device of claim 17 (See Above). Kim et al. teach wherein the second transistor (Figure 8, Element NT1. Paragraph 48) is an N-type metal-oxide-semiconductor field-effect transistor (Paragraph 47).
Kim et al. is silent with regards to wherein the first transistor and the third transistor are P-type metal-oxide-semiconductor field-effect transistors.
The examiner takes official notice that P-type metal-oxide-semiconductor field-effect transistors are well known art. It would have been obvious to a person of ordinary skill in the art to modify the transistors of Kim et al. with the well-known P-type metal-oxide-semiconductor field-effect transistors. The well-known P-type metal-oxide-semiconductor field-effect transistors could have been substituted with the transistors as taught by Kim et al. and the results would have been predictable and resulted in the first transistor and the third transistor are P-type metal-oxide-semiconductor field-effect transistors. Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Regarding Claim 19, Kim et al. in view of Sudo teach the electronic device of claim 16 (See Above). Kim et al. teach further comprising: a first switching transistor (Figure 11, Element NT5. Paragraph 81), coupled between the driver transistor (Figure 8, Element NT4. Paragraph 48) and the first electronic unit (Figure 8, Element GN. Paragraph 53); and wherein a magnitude of a current flowing through the electronic unit (Figure 8, Element GN. Paragraph 53) is modulated according to the pulse amplitude (Figure 9, Element not labeled, but is the amplitude of signal SS. Paragraph 70), and a duration of the current flowing through the electronic unit (Figure 8, Element GN. Paragraph 53) is modulated according to the pulse width (Figure 9, Element TON. Paragraph 70).
Kim et al. is silent with regards to a second electronic unit; and a second switching transistor, coupled between the driver transistor and the second electronic unit; the electronic unit being a second electronic unit.
Sudo teaches a second electronic unit (Figure 14, Elements 5 and 20. Paragraph 70); and a second switching transistor (Figure 14, Element 5. Paragraph 70), coupled between the driver transistor (Figure 14, Elements 17 and 18. Paragraph 41) and the second electronic unit (Figure 14, Elements 5 and 20. Paragraph 70); the electronic unit (Figure 14, Elements 5 and 20. Paragraph 70) being a second electronic unit.
It would have been obvious to a person of ordinary skill of the art to modify the display device of Kim et al. with the driver circuit of Sudo. The motivation to modify the teachings of Kim et al. with the Sudo is to reduce power consumption, as taught by Sudo (Paragraph 11).
Regarding Claim 20, Kim et al. in view of Sudo teach the electronic device of claim 19 (See Above). Kim et al. teach wherein the second transistor (Figure 8, Element NT1. Paragraph 48) is an N-type metal-oxide-semiconductor field-effect transistor (Paragraph 47).
Kim et al. is silent with regards to wherein the first transistor, the first switching transistor and the second switching transistor are P-type metal-oxide-semiconductor field-effect transistors.
The examiner takes official notice that P-type metal-oxide-semiconductor field-effect transistors are well known art. It would have been obvious to a person of ordinary skill in the art to modify the transistors of Kim et al. with the well-known P-type metal-oxide-semiconductor field-effect transistors. The well-known P-type metal-oxide-semiconductor field-effect transistors could have been substituted with the transistors as taught by Kim et al. and the results would have been predictable and resulted in the first transistor, the first switching transistor and the second switching transistor are P-type metal-oxide-semiconductor field-effect transistors. Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Tung et al. (U.S. Patent No. 11,361,701); Cheng (U.S. PG Pub 2022/0230580); Hashimoto (U.S. PG Pub 2022/0330401); and Hashimoto et al. (U.S. PG Pub 2023/0120265) disclose circuits that are capable of pulse width modulation and pulse amplitude modulation, similar to the instant application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW B SCHNIREL whose telephone number is (571)270-7690. The examiner can normally be reached Monday - Friday, 10 - 6 EST.
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/A.B.S/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625