Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2024-0072966, filed on 6/4/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 12, & 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagashima et al. PG Pub US 2024/0078173 A1 [hereinafter Nagashima].
Regarding claim 1, Nagashima discloses:
a memory device configured to operate in a current frequency set point (FSP) operation mode among a plurality of FSP operation modes (writing one or more values to the mode register may cause the memory to operate at a particular frequency set point and use appropriate operation parameters for the particular frequency set point [0019]);
and a system-on-chip (SoC) configured to control the memory device, wherein the memory device includes: FSP mode register sets configured to store a plurality of FSP data sets respectively corresponding to the plurality of FSP operation modes (writing one or more values to the mode register may cause the memory to operate at a particular frequency set point and use appropriate operation parameters for the particular frequency set point [0019]); and
a temperature monitoring circuit configured to monitor a temperature range of the memory device (semiconductor device 200 may include a temperature sensor 235. The temperature sensor 235 may monitor a temperature of the semiconductor device 200 [0052]),
wherein the SoC is further configured to control the current FSP operation mode based on a current operation frequency of the memory device and a current temperature range of the memory device, and wherein the plurality of FSP operation modes include a first FSP operation mode for an operation of the memory device at a first operation frequency and a first temperature range (Mode register write commands may be issued by the controller 10 to one or more of the memories 110 to control one or more operating conditions of the memories 110 [0019]), and
a second FSP operation mode for an operation of the memory device at the first operation frequency and a second temperature range higher than the first temperature range (the training operation may be performed at other times, for example, responsive to a temperature change and/or a change in operating conditions (e.g., change in frequency of operation memory 110, change in frequency of the system or data clock signals) [0030]).
Regarding claim 2 the limitations of this claim have been noted in the rejection of claim 1. Nagashima also discloses:
wherein each of the FSP data sets includes information about operating parameters of the memory device in a respective one of the FSP operation modes, and wherein the memory device further includes: a control logic circuit configured to control the operating parameters of the memory device based on a current FSP data set corresponding to the current FSP operation mode from among the FSP data sets (Mode register write commands may be issued by the controller 10 to one or more of the memories 110 to control one or more operating conditions of the memories 110…writing one or more values to the mode register may cause the memory to operate at a particular frequency set point and use appropriate operation parameters for the particular frequency set point [0019]).
Regarding claim 12 the limitations of this claim have been noted in the rejection of claim 1. Nagashima also discloses:
wherein the memory device further includes a temperature monitoring mode register configured to store temperature data, and wherein the temperature data includes information about the current temperature range of the memory device and information about whether the current temperature range is changed (The temperature sensor 235 may provide a temperature to the mode register 275, which may write a value indicative of the sense temperature to a register of the mode register 275 at regular intervals [0052]).
Regarding claim 19, Nagashima discloses:
A memory device that is configured to operate based on a current frequency set point (FSP) operation mode among a plurality of FSP operation modes, the memory device comprising: an FSP selection mode register configured to store information about the current FSP operation mode; FSP mode register sets configured to store FSP data sets respectively corresponding to the plurality of FSP operation modes (writing one or more values to the mode register may cause the memory to operate at a particular frequency set point and use appropriate operation parameters for the particular frequency set point [0019]);
a temperature monitoring mode register configured to store temperature data associated with a current temperature range of the memory device; a temperature monitoring circuit configured to monitor the current temperature range (The temperature sensor 235 may provide a temperature to the mode register 275, which may write a value indicative of the sense temperature to a register of the mode register 275 at regular intervals [0052]); and
a control logic circuit configured to control operating parameters of the memory device based on an FSP data set corresponding to the current FSP operation mode from among the FSP data sets, wherein the plurality of FSP operation modes include a first FSP operation mode for an operation of the memory device in a first temperature range, and a second FSP operation mode for an operation of the memory device in a second temperature range higher than the first temperature range, and wherein the current FSP operation mode is determined based on the temperature data (If a difference between a previously written temperature and a current temperature is above a threshold, the mode register 275 may provide a temperature signal to the command decoder 215 and/or other component of semiconductor device 200. Responsive to the signal, the semiconductor device 200 may provide an output to the memory controller indicating the temperature change. The output may be provided via one or more DQ terminals and/or another terminal. Responsive, at least in part, to the temperature signal, the memory controller may initiate the training operation [0052]).
Allowable Subject Matter
Claims 3-11 & 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art of record, Nagashima, discloses the use of FSP registers and temperature sensors to monitor and control RAM modes. However, Nagashima is using the temperature to determine if a training operation is to be performed. The objected claims limit claim interpretations from reading on Nagashima.
Claims 13-18 are allowed.
Independent claim 13, contains the allowable subject matter previously disclosed.
Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Mulani et al. PG Pub US 2024/0345743 A1 discloses that a controller may determine that if the temperature is outside a temperature range, the controller may increase or decrease the frequency at which the temperature is checked to control the temperature of the memory device.
Mahajan et al. PG Pub US 2026/0086964 A1 discloses wherein the DRAM device includes a frequency set point register that specifies operation of the DRAM device at a particular frequency of multiple possible frequencies.
Conclusion
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/SEAN D ROSSITER/ Primary Examiner, Art Unit 2133
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